diff --git a/.vs/SAM3S4B/v14/.atsuo b/.vs/SAM3S4B/v14/.atsuo index 5541542..ece7082 100644 Binary files a/.vs/SAM3S4B/v14/.atsuo and b/.vs/SAM3S4B/v14/.atsuo differ diff --git a/SAM3S4B/Debug/Makefile b/SAM3S4B/Debug/Makefile new file mode 100644 index 0000000..7593908 --- /dev/null +++ b/SAM3S4B/Debug/Makefile @@ -0,0 +1,235 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL := cmd.exe +RM := rm -rf + +USER_OBJS := + +LIBS := +PROJ := + +O_SRCS := +C_SRCS := +S_SRCS := +S_UPPER_SRCS := +OBJ_SRCS := +ASM_SRCS := +PREPROCESSING_SRCS := +OBJS := +OBJS_AS_ARGS := +C_DEPS := +C_DEPS_AS_ARGS := +EXECUTABLES := +OUTPUT_FILE_PATH := +OUTPUT_FILE_PATH_AS_ARGS := +AVR_APP_PATH :=$$$AVR_APP_PATH$$$ +QUOTE := " +ADDITIONAL_DEPENDENCIES:= +OUTPUT_FILE_DEP:= +LIB_DEP:= +LINKER_SCRIPT_DEP:= + +# Every subdirectory with source files must be described here +SUBDIRS := \ +../src/ \ +../src/ASF/ \ +../src/ASF/common/ \ +../src/ASF/common/boards/ \ +../src/ASF/common/boards/user_board/ \ +../src/ASF/common/utils/ \ +../src/ASF/common/utils/interrupt/ \ +../src/ASF/drivers \ +../src/ASF/sam/ \ +../src/ASF/sam/utils/ \ +../src/ASF/sam/utils/cmsis/ \ +../src/ASF/sam/utils/cmsis/sam3s/ \ +../src/ASF/sam/utils/cmsis/sam3s/include/ \ +../src/ASF/sam/utils/cmsis/sam3s/include/component/ \ +../src/ASF/sam/utils/cmsis/sam3s/include/instance/ \ +../src/ASF/sam/utils/cmsis/sam3s/include/pio/ \ +../src/ASF/sam/utils/cmsis/sam3s/source/ \ +../src/ASF/sam/utils/cmsis/sam3s/source/templates/ \ +../src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/ \ +../src/ASF/sam/utils/header_files/ \ +../src/ASF/sam/utils/linker_scripts/ \ +../src/ASF/sam/utils/linker_scripts/sam3s/ \ +../src/ASF/sam/utils/linker_scripts/sam3s/sam3s4/ \ +../src/ASF/sam/utils/linker_scripts/sam3s/sam3s4/gcc/ \ +../src/ASF/sam/utils/make/ \ +../src/ASF/sam/utils/preprocessor/ \ +../src/ASF/sam/utils/syscalls/ \ +../src/ASF/sam/utils/syscalls/gcc/ \ +../src/ASF/thirdparty/ \ +../src/ASF/thirdparty/CMSIS/ \ +../src/ASF/thirdparty/CMSIS/Include/ \ +../src/ASF/thirdparty/CMSIS/Lib/ \ +../src/ASF/thirdparty/CMSIS/Lib/GCC/ \ +../src/config/ + + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../src/ASF/common/boards/user_board/init.c \ +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \ +../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.c \ +../src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.c \ +../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.c \ +../src/ASF/sam/utils/syscalls/gcc/syscalls.c \ +../src/main.c + + +PREPROCESSING_SRCS += + + +ASM_SRCS += + + +OBJS += \ +src/ASF/common/boards/user_board/init.o \ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.o \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.o \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.o \ +src/ASF/sam/utils/syscalls/gcc/syscalls.o \ +src/main.o + +OBJS_AS_ARGS += \ +src/ASF/common/boards/user_board/init.o \ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.o \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.o \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.o \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.o \ +src/ASF/sam/utils/syscalls/gcc/syscalls.o \ +src/main.o + +C_DEPS += \ +src/ASF/common/boards/user_board/init.d \ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.d \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.d \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.d \ +src/ASF/sam/utils/syscalls/gcc/syscalls.d \ +src/main.d + +C_DEPS_AS_ARGS += \ +src/ASF/common/boards/user_board/init.d \ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.d \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.d \ +src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.d \ +src/ASF/sam/utils/syscalls/gcc/syscalls.d \ +src/main.d + +OUTPUT_FILE_PATH +=SAM3S4B.elf + +OUTPUT_FILE_PATH_AS_ARGS +=SAM3S4B.elf + +ADDITIONAL_DEPENDENCIES:= + +OUTPUT_FILE_DEP:= ./makedep.mk + +LIB_DEP+= + +LINKER_SCRIPT_DEP+= \ +../src/ASF/sam/utils/linker_scripts/sam3s/sam3s4/gcc/flash.ld + + +# AVR32/GNU C Compiler +src/ASF/common/boards/user_board/init.o: ../src/ASF/common/boards/user_board/init.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 6.3.1 + $(QUOTE)D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3S4B__ -DDEBUG -Dscanf=iscanf -DBOARD=USER_BOARD -DARM_MATH_CM3=true -Dprintf=iprintf -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam/utils/cmsis/sam3s/source/templates" -I"../src/ASF/sam/utils/cmsis/sam3s/include" -I"../src/ASF/common/boards/user_board" -I"../src" -I"../src/config" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 6.3.1 + $(QUOTE)D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3S4B__ -DDEBUG -Dscanf=iscanf -DBOARD=USER_BOARD -DARM_MATH_CM3=true -Dprintf=iprintf -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam/utils/cmsis/sam3s/source/templates" -I"../src/ASF/sam/utils/cmsis/sam3s/include" -I"../src/ASF/common/boards/user_board" -I"../src" -I"../src/config" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.o: ../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 6.3.1 + $(QUOTE)D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3S4B__ -DDEBUG -Dscanf=iscanf -DBOARD=USER_BOARD -DARM_MATH_CM3=true -Dprintf=iprintf -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam/utils/cmsis/sam3s/source/templates" -I"../src/ASF/sam/utils/cmsis/sam3s/include" -I"../src/ASF/common/boards/user_board" -I"../src" -I"../src/config" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.o: ../src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 6.3.1 + $(QUOTE)D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3S4B__ -DDEBUG -Dscanf=iscanf -DBOARD=USER_BOARD -DARM_MATH_CM3=true -Dprintf=iprintf -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam/utils/cmsis/sam3s/source/templates" -I"../src/ASF/sam/utils/cmsis/sam3s/include" -I"../src/ASF/common/boards/user_board" -I"../src" -I"../src/config" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.o: ../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 6.3.1 + $(QUOTE)D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3S4B__ -DDEBUG -Dscanf=iscanf -DBOARD=USER_BOARD -DARM_MATH_CM3=true -Dprintf=iprintf -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam/utils/cmsis/sam3s/source/templates" -I"../src/ASF/sam/utils/cmsis/sam3s/include" -I"../src/ASF/common/boards/user_board" -I"../src" -I"../src/config" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/ASF/sam/utils/syscalls/gcc/syscalls.o: ../src/ASF/sam/utils/syscalls/gcc/syscalls.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 6.3.1 + $(QUOTE)D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3S4B__ -DDEBUG -Dscanf=iscanf -DBOARD=USER_BOARD -DARM_MATH_CM3=true -Dprintf=iprintf -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam/utils/cmsis/sam3s/source/templates" -I"../src/ASF/sam/utils/cmsis/sam3s/include" -I"../src/ASF/common/boards/user_board" -I"../src" -I"../src/config" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + +src/main.o: ../src/main.c + @echo Building file: $< + @echo Invoking: ARM/GNU C Compiler : 6.3.1 + $(QUOTE)D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAM3S4B__ -DDEBUG -Dscanf=iscanf -DBOARD=USER_BOARD -DARM_MATH_CM3=true -Dprintf=iprintf -I"../src/ASF/common/boards" -I"../src/ASF/sam/utils" -I"../src/ASF/sam/utils/header_files" -I"../src/ASF/sam/utils/preprocessor" -I"../src/ASF/thirdparty/CMSIS/Include" -I"../src/ASF/thirdparty/CMSIS/Lib/GCC" -I"../src/ASF/common/utils" -I"../src/ASF/sam/utils/cmsis/sam3s/source/templates" -I"../src/ASF/sam/utils/cmsis/sam3s/include" -I"../src/ASF/common/boards/user_board" -I"../src" -I"../src/config" -O1 -fdata-sections -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m3 -c -pipe -fno-strict-aliasing -Wall -Wstrict-prototypes -Wmissing-prototypes -Werror-implicit-function-declaration -Wpointer-arith -std=gnu99 -ffunction-sections -fdata-sections -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -Wmain -Wparentheses -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -Wshadow -Wbad-function-cast -Wwrite-strings -Wsign-compare -Waggregate-return -Wmissing-declarations -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -Wunreachable-code -Wcast-align --param max-inline-insns-single=500 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + + + + +# AVR32/GNU Preprocessing Assembler + + + +# AVR32/GNU Assembler + + + + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +# Add inputs and outputs from these tool invocations to the build variables + +# All Target +all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES) + +$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP) + @echo Building target: $@ + @echo Invoking: ARM/GNU Linker : 6.3.1 + $(QUOTE)D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="SAM3S4B.map" -Wl,--start-group -larm_cortexM3l_math -lm -Wl,--end-group -L"../src/ASF/thirdparty/CMSIS/Lib/GCC" -Wl,--gc-sections -mcpu=cortex-m3 -Wl,--entry=Reset_Handler -Wl,--cref -mthumb -T../src/ASF/sam/utils/linker_scripts/sam3s/sam3s4/gcc/flash.ld + @echo Finished building target: $@ + "D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "SAM3S4B.elf" "SAM3S4B.bin" + "D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature "SAM3S4B.elf" "SAM3S4B.hex" + "D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "SAM3S4B.elf" "SAM3S4B.eep" || exit 0 + "D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "SAM3S4B.elf" > "SAM3S4B.lss" + "D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature "SAM3S4B.elf" "SAM3S4B.srec" + "D:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "SAM3S4B.elf" + + + + + + + +# Other Targets +clean: + -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES) + -$(RM) $(C_DEPS_AS_ARGS) + rm -rf "SAM3S4B.elf" "SAM3S4B.a" "SAM3S4B.hex" "SAM3S4B.bin" "SAM3S4B.lss" "SAM3S4B.eep" "SAM3S4B.map" "SAM3S4B.srec" + \ No newline at end of file diff --git a/SAM3S4B/Debug/SAM3S4B.bin b/SAM3S4B/Debug/SAM3S4B.bin new file mode 100644 index 0000000..7ae4050 Binary files /dev/null and b/SAM3S4B/Debug/SAM3S4B.bin differ diff --git a/SAM3S4B/Debug/SAM3S4B.eep b/SAM3S4B/Debug/SAM3S4B.eep new file mode 100644 index 0000000..e69de29 diff --git a/SAM3S4B/Debug/SAM3S4B.elf b/SAM3S4B/Debug/SAM3S4B.elf new file mode 100644 index 0000000..bd5be1c Binary files /dev/null and b/SAM3S4B/Debug/SAM3S4B.elf differ diff --git a/SAM3S4B/Debug/SAM3S4B.hex b/SAM3S4B/Debug/SAM3S4B.hex new file mode 100644 index 0000000..198a834 --- /dev/null +++ b/SAM3S4B/Debug/SAM3S4B.hex @@ -0,0 +1,126 @@ +:020000040040BA +:1000000070240020410140003F0140003F014000BA +:100010003F0140003F0140003F0140000000000060 +:100020000000000000000000000000003F01400050 +:100030003F014000000000003F0140003F01400040 +:100040003F0140003F0140003F0140003F014000B0 +:100050003F0140003F0140003F0140003F014000A0 +:100060003F0140003F0140003F0140003F01400090 +:100070003F0140003F0140003F0140003F01400080 +:100080003F0140003F0140003F0140003F01400070 +:100090003F0140003F0140003F0140003F01400060 +:1000A0003F0140003F0140003F0140003F01400050 +:1000B0003F0140003F0140003F0140003F01400040 +:1000C0003F0140003F0140003F0140003F01400030 +:1000D00010B5054C237833B9044B13B10448AFF382 +:1000E00000800123237010BD2C04002000000000BC +:1000F000800340000C4B43B10C4810B50C49AFF3E2 +:1001000000800C48036823B910BD0A48036833B95E +:100110007047094B002BF7D0BDE810401847064B3D +:10012000002BF5D0184700BF0000000080034000FE +:100130003004002080034000000000007047FEE70C +:1001400008B51C4B1C4A9A4210D01C4B194A9A42C3 +:100150000CD2013B9B1A23F00303043313441649CA +:1001600051F8040B42F8040B9A42F9D1144B154A8A +:100170009A420AD2013B9B1A23F00303043313442F +:10018000002142F8041B9342FBD10F4B23F0604245 +:1001900022F07F020D498A6003F16043B3F5404FBE +:1001A00003D28B6843F000538B60094B9847094B8F +:1001B0009847FEE700000020800340002C04002048 +:1001C0006C0400202C0400200000400000ED00E042 +:1001D000E9014000D901400008B5024B98470020D2 +:1001E00008BD00BF3D01400070B50F4E0F4D761B9E +:1001F000B61018BF002405D0013455F8043B9847C9 +:10020000A642F9D10A4E0B4D00F0A8F8761BB610A5 +:1002100018BF002406D0013455F8043B9847A64285 +:10022000F9D170BD70BD00BF680340006803400095 +:100230007003400068034000024B13B1024800F015 +:1002400005B8704700000000590240000023014635 +:100250001A46184600F01EB838B50A4C0A4D641B01 +:10026000A4100AD004F18043013B05EB8305013C57 +:1002700055F804399847002CF9D1BDE8384000F012 +:1002800077B800BF800340007C034000704700BF88 +:10029000704700BF2DE9F8432C4D06462868984664 +:1002A0000F469146FFF7F2FF294B1C68D4F84831FE +:1002B000002B3ED05A681F2A1CDC02F1010E76B1D9 +:1002C000012103EB8204C4F88890D3F8880191409F +:1002D0000843022EC3F88801C4F8088123D00232F3 +:1002E000C3F804E0286843F82270FFF7D1FF00202C +:1002F000BDE8F883174B0BB34FF4C870AFF3008021 +:100300000346D8B10020D4F848114FF0010E5860D0 +:1003100019600246C4F84831C3F88801C3F88C015B +:10032000002EDCD0CCE7D3F88C010143C3F88C114C +:10033000D5E704F5A673C4F84831BBE72868FFF792 +:10034000A7FF4FF0FF30BDE8F88300BF280400206E +:10035000580340000000000000000020F8B500BF76 +:10036000F8BC08BC9E46704739024000F5004000CA +:10037000F8B500BFF8BC08BC9E467047D1004000ED +:1003800000000000EC02002054030020BC03002009 +:10039000000000000000000000000000000000005D +:1003A000000000000000000000000000000000004D +:1003B000000000000000000000000000000000003D +:1003C000000000000000000000000000000000002D +:1003D000000000000000000000000000000000001D +:1003E000000000000000000000000000000000000D +:1003F00000000000000000000000000000000000FD +:1004000000000000000000000000000000000000EC +:1004100000000000000000000000000000000000DC +:1004200000000000000000000100000000000000CB +:100430000E33CDAB34126DE6ECDE05000B00000090 +:1004400000000000000000000000000000000000AC +:10045000000000000000000000000000000000009C +:10046000000000000000000000000000000000008C +:10047000000000000000000000000000000000007C +:10048000000000000000000000000000000000006C +:10049000000000000000000000000000000000005C +:1004A000000000000000000000000000000000004C +:1004B000000000000000000000000000000000003C +:1004C000000000000000000000000000000000002C +:1004D000000000000000000000000000000000001C +:1004E000000000000000000000000000000000000C +:1004F00000000000000000000000000000000000FC +:1005000000000000000000000000000000000000EB +:1005100000000000000000000000000000000000DB +:1005200000000000000000000000000000000000CB +:1005300000000000000000000000000000000000BB +:1005400000000000000000000000000000000000AB +:10055000000000000000000000000000000000009B +:10056000000000000000000000000000000000008B +:10057000000000000000000000000000000000007B +:10058000000000000000000000000000000000006B +:10059000000000000000000000000000000000005B +:1005A000000000000000000000000000000000004B +:1005B000000000000000000000000000000000003B +:1005C000000000000000000000000000000000002B +:1005D000000000000000000000000000000000001B +:1005E000000000000000000000000000000000000B +:1005F00000000000000000000000000000000000FB +:1006000000000000000000000000000000000000EA +:1006100000000000000000000000000000000000DA +:1006200000000000000000000000000000000000CA +:1006300000000000000000000000000000000000BA +:1006400000000000000000000000000000000000AA +:10065000000000000000000000000000000000009A +:10066000000000000000000000000000000000008A +:10067000000000000000000000000000000000007A +:10068000000000000000000000000000000000006A +:10069000000000000000000000000000000000005A +:1006A000000000000000000000000000000000004A +:1006B000000000000000000000000000000000003A +:1006C000000000000000000000000000000000002A +:1006D000000000000000000000000000000000001A +:1006E000000000000000000000000000000000000A +:1006F00000000000000000000000000000000000FA +:1007000000000000000000000000000000000000E9 +:1007100000000000000000000000000000000000D9 +:1007200000000000000000000000000000000000C9 +:1007300000000000000000000000000000000000B9 +:1007400000000000000000000000000000000000A9 +:100750000000000000000000000000000000000099 +:100760000000000000000000000000000000000089 +:100770000000000000000000000000000000000079 +:100780000000000000000000000000000000000069 +:100790000000000000000000000000000000000059 +:0C07A000000000000000000048040020E1 +:040000050040014175 +:00000001FF diff --git a/SAM3S4B/Debug/SAM3S4B.lss b/SAM3S4B/Debug/SAM3S4B.lss new file mode 100644 index 0000000..aa8081b --- /dev/null +++ b/SAM3S4B/Debug/SAM3S4B.lss @@ -0,0 +1,413 @@ + +SAM3S4B.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 00000380 00400000 00400000 00010000 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .relocate 0000042c 20000000 00400380 00020000 2**3 + CONTENTS, ALLOC, LOAD, DATA + 2 .bss 00000040 2000042c 004007ac 0002042c 2**2 + ALLOC + 3 .stack 00002004 2000046c 004007ec 0002042c 2**0 + ALLOC + 4 .ARM.attributes 00000029 00000000 00000000 0002042c 2**0 + CONTENTS, READONLY + 5 .comment 00000059 00000000 00000000 00020455 2**0 + CONTENTS, READONLY + 6 .debug_info 00002be7 00000000 00000000 000204ae 2**0 + CONTENTS, READONLY, DEBUGGING + 7 .debug_abbrev 000006ff 00000000 00000000 00023095 2**0 + CONTENTS, READONLY, DEBUGGING + 8 .debug_aranges 00000080 00000000 00000000 00023794 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_ranges 00000040 00000000 00000000 00023814 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_macro 0000ed6d 00000000 00000000 00023854 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_line 00002a81 00000000 00000000 000325c1 2**0 + CONTENTS, READONLY, DEBUGGING + 12 .debug_str 0004851d 00000000 00000000 00035042 2**0 + CONTENTS, READONLY, DEBUGGING + 13 .debug_frame 00000250 00000000 00000000 0007d560 2**2 + CONTENTS, READONLY, DEBUGGING + 14 .debug_loc 0000008b 00000000 00000000 0007d7b0 2**0 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +00400000 : + 400000: 70 24 00 20 41 01 40 00 3f 01 40 00 3f 01 40 00 p$. A.@.?.@.?.@. + 400010: 3f 01 40 00 3f 01 40 00 3f 01 40 00 00 00 00 00 ?.@.?.@.?.@..... + ... + 40002c: 3f 01 40 00 3f 01 40 00 00 00 00 00 3f 01 40 00 ?.@.?.@.....?.@. + 40003c: 3f 01 40 00 3f 01 40 00 3f 01 40 00 3f 01 40 00 ?.@.?.@.?.@.?.@. + 40004c: 3f 01 40 00 3f 01 40 00 3f 01 40 00 3f 01 40 00 ?.@.?.@.?.@.?.@. + 40005c: 3f 01 40 00 3f 01 40 00 3f 01 40 00 3f 01 40 00 ?.@.?.@.?.@.?.@. + 40006c: 3f 01 40 00 3f 01 40 00 3f 01 40 00 3f 01 40 00 ?.@.?.@.?.@.?.@. + 40007c: 3f 01 40 00 3f 01 40 00 3f 01 40 00 3f 01 40 00 ?.@.?.@.?.@.?.@. + 40008c: 3f 01 40 00 3f 01 40 00 3f 01 40 00 3f 01 40 00 ?.@.?.@.?.@.?.@. + 40009c: 3f 01 40 00 3f 01 40 00 3f 01 40 00 3f 01 40 00 ?.@.?.@.?.@.?.@. + 4000ac: 3f 01 40 00 3f 01 40 00 3f 01 40 00 3f 01 40 00 ?.@.?.@.?.@.?.@. + 4000bc: 3f 01 40 00 3f 01 40 00 3f 01 40 00 3f 01 40 00 ?.@.?.@.?.@.?.@. + 4000cc: 3f 01 40 00 ?.@. + +004000d0 <__do_global_dtors_aux>: + 4000d0: b510 push {r4, lr} + 4000d2: 4c05 ldr r4, [pc, #20] ; (4000e8 <__do_global_dtors_aux+0x18>) + 4000d4: 7823 ldrb r3, [r4, #0] + 4000d6: b933 cbnz r3, 4000e6 <__do_global_dtors_aux+0x16> + 4000d8: 4b04 ldr r3, [pc, #16] ; (4000ec <__do_global_dtors_aux+0x1c>) + 4000da: b113 cbz r3, 4000e2 <__do_global_dtors_aux+0x12> + 4000dc: 4804 ldr r0, [pc, #16] ; (4000f0 <__do_global_dtors_aux+0x20>) + 4000de: f3af 8000 nop.w + 4000e2: 2301 movs r3, #1 + 4000e4: 7023 strb r3, [r4, #0] + 4000e6: bd10 pop {r4, pc} + 4000e8: 2000042c .word 0x2000042c + 4000ec: 00000000 .word 0x00000000 + 4000f0: 00400380 .word 0x00400380 + +004000f4 : + 4000f4: 4b0c ldr r3, [pc, #48] ; (400128 ) + 4000f6: b143 cbz r3, 40010a + 4000f8: 480c ldr r0, [pc, #48] ; (40012c ) + 4000fa: b510 push {r4, lr} + 4000fc: 490c ldr r1, [pc, #48] ; (400130 ) + 4000fe: f3af 8000 nop.w + 400102: 480c ldr r0, [pc, #48] ; (400134 ) + 400104: 6803 ldr r3, [r0, #0] + 400106: b923 cbnz r3, 400112 + 400108: bd10 pop {r4, pc} + 40010a: 480a ldr r0, [pc, #40] ; (400134 ) + 40010c: 6803 ldr r3, [r0, #0] + 40010e: b933 cbnz r3, 40011e + 400110: 4770 bx lr + 400112: 4b09 ldr r3, [pc, #36] ; (400138 ) + 400114: 2b00 cmp r3, #0 + 400116: d0f7 beq.n 400108 + 400118: e8bd 4010 ldmia.w sp!, {r4, lr} + 40011c: 4718 bx r3 + 40011e: 4b06 ldr r3, [pc, #24] ; (400138 ) + 400120: 2b00 cmp r3, #0 + 400122: d0f5 beq.n 400110 + 400124: 4718 bx r3 + 400126: bf00 nop + 400128: 00000000 .word 0x00000000 + 40012c: 00400380 .word 0x00400380 + 400130: 20000430 .word 0x20000430 + 400134: 00400380 .word 0x00400380 + 400138: 00000000 .word 0x00000000 + +0040013c : +#include +#include +#include + +void board_init(void) +{ + 40013c: 4770 bx lr + +0040013e : + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + 40013e: e7fe b.n 40013e + +00400140 : +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + 400140: b508 push {r3, lr} + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + 400142: 4b1c ldr r3, [pc, #112] ; (4001b4 ) + 400144: 4a1c ldr r2, [pc, #112] ; (4001b8 ) + 400146: 429a cmp r2, r3 + 400148: d010 beq.n 40016c + for (; pDest < &_erelocate;) { + 40014a: 4b1c ldr r3, [pc, #112] ; (4001bc ) + 40014c: 4a19 ldr r2, [pc, #100] ; (4001b4 ) + 40014e: 429a cmp r2, r3 + 400150: d20c bcs.n 40016c + 400152: 3b01 subs r3, #1 + 400154: 1a9b subs r3, r3, r2 + 400156: f023 0303 bic.w r3, r3, #3 + 40015a: 3304 adds r3, #4 + 40015c: 4413 add r3, r2 + 40015e: 4916 ldr r1, [pc, #88] ; (4001b8 ) + *pDest++ = *pSrc++; + 400160: f851 0b04 ldr.w r0, [r1], #4 + 400164: f842 0b04 str.w r0, [r2], #4 + for (; pDest < &_erelocate;) { + 400168: 429a cmp r2, r3 + 40016a: d1f9 bne.n 400160 + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + 40016c: 4b14 ldr r3, [pc, #80] ; (4001c0 ) + 40016e: 4a15 ldr r2, [pc, #84] ; (4001c4 ) + 400170: 429a cmp r2, r3 + 400172: d20a bcs.n 40018a + 400174: 3b01 subs r3, #1 + 400176: 1a9b subs r3, r3, r2 + 400178: f023 0303 bic.w r3, r3, #3 + 40017c: 3304 adds r3, #4 + 40017e: 4413 add r3, r2 + *pDest++ = 0; + 400180: 2100 movs r1, #0 + 400182: f842 1b04 str.w r1, [r2], #4 + for (pDest = &_szero; pDest < &_ezero;) { + 400186: 4293 cmp r3, r2 + 400188: d1fb bne.n 400182 + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + 40018a: 4b0f ldr r3, [pc, #60] ; (4001c8 ) + 40018c: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000 + 400190: f022 027f bic.w r2, r2, #127 ; 0x7f + 400194: 490d ldr r1, [pc, #52] ; (4001cc ) + 400196: 608a str r2, [r1, #8] + + if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) { + 400198: f103 4360 add.w r3, r3, #3758096384 ; 0xe0000000 + 40019c: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 4001a0: d203 bcs.n 4001aa + SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos; + 4001a2: 688b ldr r3, [r1, #8] + 4001a4: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 4001a8: 608b str r3, [r1, #8] + } + + /* Initialize the C library */ + __libc_init_array(); + 4001aa: 4b09 ldr r3, [pc, #36] ; (4001d0 ) + 4001ac: 4798 blx r3 + + /* Branch to main function */ + main(); + 4001ae: 4b09 ldr r3, [pc, #36] ; (4001d4 ) + 4001b0: 4798 blx r3 + 4001b2: e7fe b.n 4001b2 + 4001b4: 20000000 .word 0x20000000 + 4001b8: 00400380 .word 0x00400380 + 4001bc: 2000042c .word 0x2000042c + 4001c0: 2000046c .word 0x2000046c + 4001c4: 2000042c .word 0x2000042c + 4001c8: 00400000 .word 0x00400000 + 4001cc: e000ed00 .word 0xe000ed00 + 4001d0: 004001e9 .word 0x004001e9 + 4001d4: 004001d9 .word 0x004001d9 + +004001d8
: + * Support and FAQ: visit Microchip Support + */ +#include + +int main (void) +{ + 4001d8: b508 push {r3, lr} + /* Insert system clock initialization code here (sysclk_init()). */ + + board_init(); + 4001da: 4b02 ldr r3, [pc, #8] ; (4001e4 ) + 4001dc: 4798 blx r3 + + /* Insert application code here, after the board has been initialized. */ +} + 4001de: 2000 movs r0, #0 + 4001e0: bd08 pop {r3, pc} + 4001e2: bf00 nop + 4001e4: 0040013d .word 0x0040013d + +004001e8 <__libc_init_array>: + 4001e8: b570 push {r4, r5, r6, lr} + 4001ea: 4e0f ldr r6, [pc, #60] ; (400228 <__libc_init_array+0x40>) + 4001ec: 4d0f ldr r5, [pc, #60] ; (40022c <__libc_init_array+0x44>) + 4001ee: 1b76 subs r6, r6, r5 + 4001f0: 10b6 asrs r6, r6, #2 + 4001f2: bf18 it ne + 4001f4: 2400 movne r4, #0 + 4001f6: d005 beq.n 400204 <__libc_init_array+0x1c> + 4001f8: 3401 adds r4, #1 + 4001fa: f855 3b04 ldr.w r3, [r5], #4 + 4001fe: 4798 blx r3 + 400200: 42a6 cmp r6, r4 + 400202: d1f9 bne.n 4001f8 <__libc_init_array+0x10> + 400204: 4e0a ldr r6, [pc, #40] ; (400230 <__libc_init_array+0x48>) + 400206: 4d0b ldr r5, [pc, #44] ; (400234 <__libc_init_array+0x4c>) + 400208: f000 f8a8 bl 40035c <_init> + 40020c: 1b76 subs r6, r6, r5 + 40020e: 10b6 asrs r6, r6, #2 + 400210: bf18 it ne + 400212: 2400 movne r4, #0 + 400214: d006 beq.n 400224 <__libc_init_array+0x3c> + 400216: 3401 adds r4, #1 + 400218: f855 3b04 ldr.w r3, [r5], #4 + 40021c: 4798 blx r3 + 40021e: 42a6 cmp r6, r4 + 400220: d1f9 bne.n 400216 <__libc_init_array+0x2e> + 400222: bd70 pop {r4, r5, r6, pc} + 400224: bd70 pop {r4, r5, r6, pc} + 400226: bf00 nop + 400228: 00400368 .word 0x00400368 + 40022c: 00400368 .word 0x00400368 + 400230: 00400370 .word 0x00400370 + 400234: 00400368 .word 0x00400368 + +00400238 : + 400238: 4b02 ldr r3, [pc, #8] ; (400244 ) + 40023a: b113 cbz r3, 400242 + 40023c: 4802 ldr r0, [pc, #8] ; (400248 ) + 40023e: f000 b805 b.w 40024c + 400242: 4770 bx lr + 400244: 00000000 .word 0x00000000 + 400248: 00400259 .word 0x00400259 + +0040024c : + 40024c: 2300 movs r3, #0 + 40024e: 4601 mov r1, r0 + 400250: 461a mov r2, r3 + 400252: 4618 mov r0, r3 + 400254: f000 b81e b.w 400294 <__register_exitproc> + +00400258 <__libc_fini_array>: + 400258: b538 push {r3, r4, r5, lr} + 40025a: 4c0a ldr r4, [pc, #40] ; (400284 <__libc_fini_array+0x2c>) + 40025c: 4d0a ldr r5, [pc, #40] ; (400288 <__libc_fini_array+0x30>) + 40025e: 1b64 subs r4, r4, r5 + 400260: 10a4 asrs r4, r4, #2 + 400262: d00a beq.n 40027a <__libc_fini_array+0x22> + 400264: f104 4380 add.w r3, r4, #1073741824 ; 0x40000000 + 400268: 3b01 subs r3, #1 + 40026a: eb05 0583 add.w r5, r5, r3, lsl #2 + 40026e: 3c01 subs r4, #1 + 400270: f855 3904 ldr.w r3, [r5], #-4 + 400274: 4798 blx r3 + 400276: 2c00 cmp r4, #0 + 400278: d1f9 bne.n 40026e <__libc_fini_array+0x16> + 40027a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 40027e: f000 b877 b.w 400370 <_fini> + 400282: bf00 nop + 400284: 00400380 .word 0x00400380 + 400288: 0040037c .word 0x0040037c + +0040028c <__retarget_lock_acquire_recursive>: + 40028c: 4770 bx lr + 40028e: bf00 nop + +00400290 <__retarget_lock_release_recursive>: + 400290: 4770 bx lr + 400292: bf00 nop + +00400294 <__register_exitproc>: + 400294: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 400298: 4d2c ldr r5, [pc, #176] ; (40034c <__register_exitproc+0xb8>) + 40029a: 4606 mov r6, r0 + 40029c: 6828 ldr r0, [r5, #0] + 40029e: 4698 mov r8, r3 + 4002a0: 460f mov r7, r1 + 4002a2: 4691 mov r9, r2 + 4002a4: f7ff fff2 bl 40028c <__retarget_lock_acquire_recursive> + 4002a8: 4b29 ldr r3, [pc, #164] ; (400350 <__register_exitproc+0xbc>) + 4002aa: 681c ldr r4, [r3, #0] + 4002ac: f8d4 3148 ldr.w r3, [r4, #328] ; 0x148 + 4002b0: 2b00 cmp r3, #0 + 4002b2: d03e beq.n 400332 <__register_exitproc+0x9e> + 4002b4: 685a ldr r2, [r3, #4] + 4002b6: 2a1f cmp r2, #31 + 4002b8: dc1c bgt.n 4002f4 <__register_exitproc+0x60> + 4002ba: f102 0e01 add.w lr, r2, #1 + 4002be: b176 cbz r6, 4002de <__register_exitproc+0x4a> + 4002c0: 2101 movs r1, #1 + 4002c2: eb03 0482 add.w r4, r3, r2, lsl #2 + 4002c6: f8c4 9088 str.w r9, [r4, #136] ; 0x88 + 4002ca: f8d3 0188 ldr.w r0, [r3, #392] ; 0x188 + 4002ce: 4091 lsls r1, r2 + 4002d0: 4308 orrs r0, r1 + 4002d2: 2e02 cmp r6, #2 + 4002d4: f8c3 0188 str.w r0, [r3, #392] ; 0x188 + 4002d8: f8c4 8108 str.w r8, [r4, #264] ; 0x108 + 4002dc: d023 beq.n 400326 <__register_exitproc+0x92> + 4002de: 3202 adds r2, #2 + 4002e0: f8c3 e004 str.w lr, [r3, #4] + 4002e4: 6828 ldr r0, [r5, #0] + 4002e6: f843 7022 str.w r7, [r3, r2, lsl #2] + 4002ea: f7ff ffd1 bl 400290 <__retarget_lock_release_recursive> + 4002ee: 2000 movs r0, #0 + 4002f0: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 4002f4: 4b17 ldr r3, [pc, #92] ; (400354 <__register_exitproc+0xc0>) + 4002f6: b30b cbz r3, 40033c <__register_exitproc+0xa8> + 4002f8: f44f 70c8 mov.w r0, #400 ; 0x190 + 4002fc: f3af 8000 nop.w + 400300: 4603 mov r3, r0 + 400302: b1d8 cbz r0, 40033c <__register_exitproc+0xa8> + 400304: 2000 movs r0, #0 + 400306: f8d4 1148 ldr.w r1, [r4, #328] ; 0x148 + 40030a: f04f 0e01 mov.w lr, #1 + 40030e: 6058 str r0, [r3, #4] + 400310: 6019 str r1, [r3, #0] + 400312: 4602 mov r2, r0 + 400314: f8c4 3148 str.w r3, [r4, #328] ; 0x148 + 400318: f8c3 0188 str.w r0, [r3, #392] ; 0x188 + 40031c: f8c3 018c str.w r0, [r3, #396] ; 0x18c + 400320: 2e00 cmp r6, #0 + 400322: d0dc beq.n 4002de <__register_exitproc+0x4a> + 400324: e7cc b.n 4002c0 <__register_exitproc+0x2c> + 400326: f8d3 018c ldr.w r0, [r3, #396] ; 0x18c + 40032a: 4301 orrs r1, r0 + 40032c: f8c3 118c str.w r1, [r3, #396] ; 0x18c + 400330: e7d5 b.n 4002de <__register_exitproc+0x4a> + 400332: f504 73a6 add.w r3, r4, #332 ; 0x14c + 400336: f8c4 3148 str.w r3, [r4, #328] ; 0x148 + 40033a: e7bb b.n 4002b4 <__register_exitproc+0x20> + 40033c: 6828 ldr r0, [r5, #0] + 40033e: f7ff ffa7 bl 400290 <__retarget_lock_release_recursive> + 400342: f04f 30ff mov.w r0, #4294967295 + 400346: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 40034a: bf00 nop + 40034c: 20000428 .word 0x20000428 + 400350: 00400358 .word 0x00400358 + 400354: 00000000 .word 0x00000000 + +00400358 <_global_impure_ptr>: + 400358: 20000000 ... + +0040035c <_init>: + 40035c: b5f8 push {r3, r4, r5, r6, r7, lr} + 40035e: bf00 nop + 400360: bcf8 pop {r3, r4, r5, r6, r7} + 400362: bc08 pop {r3} + 400364: 469e mov lr, r3 + 400366: 4770 bx lr + +00400368 <__init_array_start>: + 400368: 00400239 .word 0x00400239 + +0040036c <__frame_dummy_init_array_entry>: + 40036c: 004000f5 ..@. + +00400370 <_fini>: + 400370: b5f8 push {r3, r4, r5, r6, r7, lr} + 400372: bf00 nop + 400374: bcf8 pop {r3, r4, r5, r6, r7} + 400376: bc08 pop {r3} + 400378: 469e mov lr, r3 + 40037a: 4770 bx lr + +0040037c <__fini_array_start>: + 40037c: 004000d1 .word 0x004000d1 diff --git a/SAM3S4B/Debug/SAM3S4B.map b/SAM3S4B/Debug/SAM3S4B.map new file mode 100644 index 0000000..7ea2ded --- /dev/null +++ b/SAM3S4B/Debug/SAM3S4B.map @@ -0,0 +1,2038 @@ +Archive member included to satisfy reference by file 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src/ASF/common/boards/user_board/init.o + src/main.o +cpu_irq_enter_critical src/ASF/common/utils/interrupt/interrupt_sam_nvic.o +cpu_irq_leave_critical src/ASF/common/utils/interrupt/interrupt_sam_nvic.o +exception_table src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.o +exit d:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc.a(lib_a-exit.o) + d:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o +free d:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc.a(lib_a-__call_atexit.o) +g_interrupt_enabled src/ASF/common/utils/interrupt/interrupt_sam_nvic.o +hardware_init_hook d:/program files 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Do not edit or delete the file +################################################################################ + +src\ASF\common\boards\user_board\init.c + +src\ASF\common\utils\interrupt\interrupt_sam_nvic.c + +src\ASF\sam\utils\cmsis\sam3s\source\templates\exceptions.c + +src\ASF\sam\utils\cmsis\sam3s\source\templates\gcc\startup_sam3s.c + +src\ASF\sam\utils\cmsis\sam3s\source\templates\system_sam3s.c + +src\ASF\sam\utils\syscalls\gcc\syscalls.c + +src\main.c + diff --git a/SAM3S4B/Debug/src/ASF/common/boards/user_board/init.d b/SAM3S4B/Debug/src/ASF/common/boards/user_board/init.d new file mode 100644 index 0000000..288ffe3 --- /dev/null +++ b/SAM3S4B/Debug/src/ASF/common/boards/user_board/init.d @@ -0,0 +1,340 @@ +src/ASF/common/boards/user_board/init.d \ + src/ASF/common/boards/user_board/init.o: \ + ../src/ASF/common/boards/user_board/init.c ../src/asf.h \ + ../src/ASF/sam/utils/compiler.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \ + ../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/utils/status_codes.h \ + ../src/ASF/common/boards/user_board/user_board.h \ + ../src/config/conf_board.h ../src/ASF/common/boards/board.h \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.h + +../src/asf.h: + +../src/ASF/sam/utils/compiler.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h: + +d:\program\ files\ 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+../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + 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(x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/utils/status_codes.h: + +../src/ASF/common/boards/user_board/user_board.h: + +../src/config/conf_board.h: + +../src/ASF/common/boards/board.h: + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.h: diff --git a/SAM3S4B/Debug/src/ASF/common/boards/user_board/init.o b/SAM3S4B/Debug/src/ASF/common/boards/user_board/init.o new file mode 100644 index 0000000..82d3500 Binary files /dev/null and b/SAM3S4B/Debug/src/ASF/common/boards/user_board/init.o differ diff --git a/SAM3S4B/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d b/SAM3S4B/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d new file mode 100644 index 0000000..8ab0d1d --- /dev/null +++ b/SAM3S4B/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.d @@ -0,0 +1,327 @@ +src/ASF/common/utils/interrupt/interrupt_sam_nvic.d \ + src/ASF/common/utils/interrupt/interrupt_sam_nvic.o: \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.c \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/utils/compiler.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \ + ../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/utils/compiler.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h: + +../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h: + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/SAM3S4B/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.o b/SAM3S4B/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.o new file mode 100644 index 0000000..11f84a2 Binary files /dev/null and b/SAM3S4B/Debug/src/ASF/common/utils/interrupt/interrupt_sam_nvic.o differ diff --git a/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.d b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.d new file mode 100644 index 0000000..745d8a3 --- /dev/null +++ b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.d @@ -0,0 +1,327 @@ +src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.d \ + src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.o: \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.c \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \ + ../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h \ + ../src/ASF/sam/utils/compiler.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h: + +../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h: + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h: + +../src/ASF/sam/utils/compiler.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h: diff --git a/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.o b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.o new file mode 100644 index 0000000..295ff23 Binary files /dev/null and b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.o differ diff --git a/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.d b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.d new file mode 100644 index 0000000..4cdeb7f --- /dev/null +++ b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.d @@ -0,0 +1,327 @@ +src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.d \ + src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.o: \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.c \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \ + ../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h \ + ../src/ASF/sam/utils/compiler.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h: + +../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h: + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h: + +../src/ASF/sam/utils/compiler.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h: diff --git a/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.o b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.o new file mode 100644 index 0000000..731fb70 Binary files /dev/null and b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/gcc/startup_sam3s.o differ diff --git a/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.d b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.d new file mode 100644 index 0000000..d7e4b7d --- /dev/null +++ b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.d @@ -0,0 +1,327 @@ +src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.d \ + src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.o: \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.c \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/sam/utils/compiler.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \ + ../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/sam/utils/compiler.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h: + +../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h: + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + 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(x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: diff --git a/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.o b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.o new file mode 100644 index 0000000..54d5e90 Binary files /dev/null and b/SAM3S4B/Debug/src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.o differ diff --git a/SAM3S4B/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.d b/SAM3S4B/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.d new file mode 100644 index 0000000..014950d --- /dev/null +++ b/SAM3S4B/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.d @@ -0,0 +1,99 @@ +src/ASF/sam/utils/syscalls/gcc/syscalls.d \ + src/ASF/sam/utils/syscalls/gcc/syscalls.o: \ + ../src/ASF/sam/utils/syscalls/gcc/syscalls.c \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + 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(x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stat.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\time.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\time.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h: diff --git a/SAM3S4B/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.o b/SAM3S4B/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.o new file mode 100644 index 0000000..1ce3d26 Binary files /dev/null and b/SAM3S4B/Debug/src/ASF/sam/utils/syscalls/gcc/syscalls.o differ diff --git a/SAM3S4B/Debug/src/main.d b/SAM3S4B/Debug/src/main.d new file mode 100644 index 0000000..15962cd --- /dev/null +++ b/SAM3S4B/Debug/src/main.d @@ -0,0 +1,338 @@ +src/main.d src/main.o: ../src/main.c ../src/asf.h \ + ../src/ASF/sam/utils/compiler.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \ + ../src/ASF/common/utils/parts.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/preprocessor/tpaste.h \ + ../src/ASF/sam/utils/preprocessor/stringz.h \ + ../src/ASF/sam/utils/preprocessor/mrepeat.h \ + ../src/ASF/sam/utils/preprocessor/preprocessor.h \ + ../src/ASF/sam/utils/header_files/io.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \ + ../src/ASF/thirdparty/CMSIS/Include/core_cm3.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h \ + ../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h \ + ../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h \ + ../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \ + d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \ + ../src/ASF/common/utils/interrupt.h \ + ../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h \ + ../src/ASF/sam/utils/status_codes.h \ + ../src/ASF/common/boards/user_board/user_board.h \ + ../src/config/conf_board.h ../src/ASF/common/boards/board.h \ + ../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.h + +../src/asf.h: + +../src/ASF/sam/utils/compiler.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h: + +../src/ASF/common/utils/parts.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/preprocessor/tpaste.h: + +../src/ASF/sam/utils/preprocessor/stringz.h: + +../src/ASF/sam/utils/preprocessor/mrepeat.h: + +../src/ASF/sam/utils/preprocessor/preprocessor.h: + +../src/ASF/sam/utils/header_files/io.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/sam3s4b.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h: + +../src/ASF/thirdparty/CMSIS/Include/core_cm3.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_version.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_compiler.h: + +../src/ASF/thirdparty/CMSIS/Include/cmsis_gcc.h: + +../src/ASF/thirdparty/CMSIS/Include/mpu_armv7.h: + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/system_sam3s.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pdc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pio.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_tc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_twi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_uart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_usart.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/component/component_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_hsmci.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_ssc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_spi.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_tc0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_twi1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pwm.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_usart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_udp.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_adc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_dacc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_acc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_crccu.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_matrix.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pmc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart0.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_chipid.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_uart1.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_efc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_pioa.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_piob.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rstc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_supc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_wdt.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_rtc.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/instance/instance_gpbr.h: + +../src/ASF/sam/utils/cmsis/sam3s/include/pio/pio_sam3s4b.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h: + +d:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h: + +../src/ASF/common/utils/interrupt.h: + +../src/ASF/common/utils/interrupt/interrupt_sam_nvic.h: + +../src/ASF/sam/utils/status_codes.h: + +../src/ASF/common/boards/user_board/user_board.h: + +../src/config/conf_board.h: + +../src/ASF/common/boards/board.h: + +../src/ASF/sam/utils/cmsis/sam3s/source/templates/exceptions.h: diff --git a/SAM3S4B/Debug/src/main.o b/SAM3S4B/Debug/src/main.o new file mode 100644 index 0000000..d25904c Binary files /dev/null and b/SAM3S4B/Debug/src/main.o differ diff --git a/SAM3S4B/SAM3S4B.cproj b/SAM3S4B/SAM3S4B.cproj index 7cf9719..128b829 100644 --- a/SAM3S4B/SAM3S4B.cproj +++ b/SAM3S4B/SAM3S4B.cproj @@ -30,134 +30,134 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -345,6 +345,13 @@ + + + + + + + diff --git a/SAM3S4B/src/ASF/drivers1/efc/efc.c b/SAM3S4B/src/ASF/drivers1/efc/efc.c new file mode 100644 index 0000000..d9a067b --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/efc/efc.c @@ -0,0 +1,400 @@ +/** + * \file + * + * \brief Enhanced Embedded Flash Controller (EEFC) driver for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "efc.h" +#include "ssc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_efc_group Enhanced Embedded Flash Controller (EEFC) + * + * The Enhanced Embedded Flash Controller ensures the interface of the Flash + * block with the 32-bit internal bus. + * + * @{ + */ + +/* Address definition for read operation */ +#if (SAM3XA || SAM3U4 || SAM4SD16 || SAM4SD32) +# define READ_BUFF_ADDR0 IFLASH0_ADDR +# define READ_BUFF_ADDR1 IFLASH1_ADDR +#elif (SAM3S || SAM3N || SAM4E || SAM4N) +# define READ_BUFF_ADDR IFLASH_ADDR +#elif (SAM3U || SAM4S) +# define READ_BUFF_ADDR IFLASH0_ADDR +#else +# warning Only reading unique ID for sam3/4 is implemented. +#endif + +/* Flash Writing Protection Key */ +#define FWP_KEY 0x5Au + +#if (SAM4S || SAM4E || SAM4N) +#define EEFC_FCR_FCMD(value) \ + ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR) +#else +#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE) +#endif + +//uint32_t ul_rc; + +/* + * Local function declaration. + * Because they are RAM functions, they need 'extern' declaration. + */ +extern void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr); +extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr); + +/** + * \brief Initialize the EFC controller. + * + * \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. + * \param ul_fws The number of wait states in cycle (no shift). + * + * \return 0 if successful. + */ +uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws) +{ + efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws)); + return EFC_RC_OK; +} + +/** + * \brief Enable the flash ready interrupt. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_enable_frdy_interrupt(Efc *p_efc) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR; + + efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FRDY); +} + +/** + * \brief Disable the flash ready interrupt. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_disable_frdy_interrupt(Efc *p_efc) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR; + + efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_FRDY)); +} + +/** + * \brief Set flash access mode. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. + */ +void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FAM); + + efc_write_fmr(p_efc, ul_fmr | ul_mode); +} + +/** + * \brief Get flash access mode. + * + * \param p_efc Pointer to an EFC instance. + * + * \return 0 for 128-bit or EEFC_FMR_FAM for 64-bit. + */ +uint32_t efc_get_flash_access_mode(Efc *p_efc) +{ + return (p_efc->EEFC_FMR & EEFC_FMR_FAM); +} + +/** + * \brief Set flash wait state. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_fws The number of wait states in cycle (no shift). + */ +void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk); + + efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws)); +} + +/** + * \brief Get flash wait state. + * + * \param p_efc Pointer to an EFC instance. + * + * \return The number of wait states in cycle (no shift). + */ +uint32_t efc_get_wait_state(Efc *p_efc) +{ + return ((p_efc->EEFC_FMR & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos); +} + +/** + * \brief Perform the given command and wait until its completion (or an error). + * + * \note Unique ID commands are not supported, use efc_read_unique_id. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_command Command to perform. + * \param ul_argument Optional command argument. + * + * \note This function will automatically choose to use IAP function. + * + * \return 0 if successful, otherwise returns an error code. + */ +uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command, + uint32_t ul_argument) +{ + //unsigned int status; + + /* Unique ID commands are not supported. */ + if (ul_command == EFC_FCMD_STUI || ul_command == EFC_FCMD_SPUI) { + return EFC_RC_NOT_SUPPORT; + } + +#if (SAM3XA || SAM3U4) + /* Use IAP function with 2 parameters in ROM. */ + static uint32_t(*iap_perform_command) (uint32_t, uint32_t); + uint32_t ul_efc_nb = (p_efc == EFC0) ? 0 : 1; + + iap_perform_command = + (uint32_t(*)(uint32_t, uint32_t)) + *((uint32_t *) CHIP_FLASH_IAP_ADDRESS); + iap_perform_command(ul_efc_nb, + EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); + return (p_efc->EEFC_FSR & EEFC_ERROR_FLAGS); + +#elif (SAM3N || SAM3S || SAM4S || SAM3U || SAM4E || SAM4N) + /* Use IAP function with 2 parameter in ROM. */ + static uint32_t(*iap_perform_command) (uint32_t, uint32_t); + + iap_perform_command = + (uint32_t(*)(uint32_t, uint32_t)) + *((uint32_t *) CHIP_FLASH_IAP_ADDRESS); + + +#if SAM4S + uint32_t ul_efc_nb = (p_efc == EFC0) ? 0 : 1; + iap_perform_command(ul_efc_nb, + EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); +#elif SAM4E || SAM4N + iap_perform_command(0, + EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); +#else + iap_perform_command(0, + EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); +#endif + return (p_efc->EEFC_FSR & EEFC_ERROR_FLAGS); +#else + /* Use RAM Function. */ + return iap_perform_command(0, + EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); + +#endif +} + +/** + * \brief Get the current status of the EEFC. + * + * \note This function clears the value of some status bits (FLOCKE, FCMDE). + * + * \param p_efc Pointer to an EFC instance. + * + * \return The current status. + */ +uint32_t efc_get_status(Efc *p_efc) +{ + return p_efc->EEFC_FSR; +} + +/** + * \brief Get the result of the last executed command. + * + * \param p_efc Pointer to an EFC instance. + * + * \return The result of the last executed command. + */ +uint32_t efc_get_result(Efc *p_efc) +{ + return p_efc->EEFC_FRR; +} + +/** + * \brief Perform read sequence. Supported sequences are read Unique ID and + * read User Signature + * + * \param p_efc Pointer to an EFC instance. + * \param ul_cmd_st Start command to perform. + * \param ul_cmd_sp Stop command to perform. + * \param p_ul_buf Pointer to an data buffer. + * \param ul_size Buffer size. + * + * \return 0 if successful, otherwise returns an error code. + */ +RAMFUNC +uint32_t efc_perform_read_sequence(Efc *p_efc, + uint32_t ul_cmd_st, uint32_t ul_cmd_sp, + uint32_t *p_ul_buf, uint32_t ul_size) +{ + volatile uint32_t ul_status; + uint32_t ul_cnt; + +#if (SAM3U4 || SAM3XA || SAM4SD16 || SAM4SD32) + uint32_t *p_ul_data = + (uint32_t *) ((p_efc == EFC0) ? + READ_BUFF_ADDR0 : READ_BUFF_ADDR1); +#elif (SAM3S || SAM4S || SAM3N || SAM3U || SAM4E || SAM4N) + uint32_t *p_ul_data = (uint32_t *) READ_BUFF_ADDR; +#else + return EFC_RC_NOT_SUPPORT; +#endif + + if (p_ul_buf == NULL) { + return EFC_RC_INVALID; + } + + p_efc->EEFC_FMR |= (0x1u << 16); + + /* Send the Start Read command */ +#if (SAM4S || SAM4E || SAM4N) + p_efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) + | EEFC_FCR_FCMD(ul_cmd_st); +#else + p_efc->EEFC_FCR = EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) + | EEFC_FCR_FCMD(ul_cmd_st); +#endif + /* Wait for the FRDY bit in the Flash Programming Status Register + * (EEFC_FSR) falls. + */ + do { + ul_status = p_efc->EEFC_FSR; + } while ((ul_status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY); + + /* The data is located in the first address of the Flash + * memory mapping. + */ + for (ul_cnt = 0; ul_cnt < ul_size; ul_cnt++) { + p_ul_buf[ul_cnt] = p_ul_data[ul_cnt]; + } + + /* To stop the read mode */ + p_efc->EEFC_FCR = +#if (SAM4S || SAM4E || SAM4N) + EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) | + EEFC_FCR_FCMD(ul_cmd_sp); +#else + EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) | + EEFC_FCR_FCMD(ul_cmd_sp); +#endif + /* Wait for the FRDY bit in the Flash Programming Status Register (EEFC_FSR) + * rises. + */ + do { + ul_status = p_efc->EEFC_FSR; + } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); + + p_efc->EEFC_FMR &= ~(0x1u << 16); + + return EFC_RC_OK; +} + +/** + * \brief Set mode register. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_fmr Value of mode register + */ +RAMFUNC +void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr) +{ + p_efc->EEFC_FMR = ul_fmr; +} + +/** + * \brief Perform command. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_fcr Flash command. + * + * \return The current status. + */ +RAMFUNC +uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr) +{ + volatile uint32_t ul_status; + + p_efc->EEFC_FCR = ul_fcr; + + do { + ul_status = p_efc->EEFC_FSR; + } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); + + return (ul_status & EEFC_ERROR_FLAGS); +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/SAM3S4B/src/ASF/drivers1/efc/efc.h b/SAM3S4B/src/ASF/drivers1/efc/efc.h new file mode 100644 index 0000000..f4105d0 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/efc/efc.h @@ -0,0 +1,135 @@ +/** + * \file + * + * \brief Embedded Flash Controller (EFC) driver for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef EFC_H_INCLUDED +#define EFC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/*! \name EFC return codes */ +//! @{ +typedef enum efc_rc { + EFC_RC_OK = 0, //!< Operation OK + EFC_RC_YES = 0, //!< Yes + EFC_RC_NO = 1, //!< No + EFC_RC_ERROR = 1, //!< General error + EFC_RC_INVALID, //!< Invalid argument input + EFC_RC_NOT_SUPPORT = 0xFFFFFFFF //!< Operation is not supported +} efc_rc_t; +//! @} + +/*! \name EFC command */ +//! @{ +#define EFC_FCMD_GETD 0x00 //!< Get Flash Descriptor +#define EFC_FCMD_WP 0x01 //!< Write page +#define EFC_FCMD_WPL 0x02 //!< Write page and lock +#define EFC_FCMD_EWP 0x03 //!< Erase page and write page +#define EFC_FCMD_EWPL 0x04 //!< Erase page and write page then lock +#define EFC_FCMD_EA 0x05 //!< Erase all +#if (SAM3SD8) +#define EFC_FCMD_EPL 0x06 //!< Erase plane +#endif +#if (SAM4S || SAM4E || SAM4N) +#define EFC_FCMD_EPA 0x07 //!< Erase pages +#endif +#define EFC_FCMD_SLB 0x08 //!< Set Lock Bit +#define EFC_FCMD_CLB 0x09 //!< Clear Lock Bit +#define EFC_FCMD_GLB 0x0A //!< Get Lock Bit +#define EFC_FCMD_SGPB 0x0B //!< Set GPNVM Bit +#define EFC_FCMD_CGPB 0x0C //!< Clear GPNVM Bit +#define EFC_FCMD_GGPB 0x0D //!< Get GPNVM Bit +#define EFC_FCMD_STUI 0x0E //!< Start unique ID +#define EFC_FCMD_SPUI 0x0F //!< Stop unique ID +#if (!SAM3U && !SAM3SD8 && !SAM3S8) +#define EFC_FCMD_GCALB 0x10 //!< Get CALIB Bit +#endif +#if (SAM4S || SAM4E || SAM4N) +#define EFC_FCMD_ES 0x11 //!< Erase sector +#define EFC_FCMD_WUS 0x12 //!< Write user signature +#define EFC_FCMD_EUS 0x13 //!< Erase user signature +#define EFC_FCMD_STUS 0x14 //!< Start read user signature +#define EFC_FCMD_SPUS 0x15 //!< Stop read user signature +#endif +//! @} + +/*! The IAP function entry address */ +#define CHIP_FLASH_IAP_ADDRESS (IROM_ADDR + 8) + +/*! \name EFC access mode */ +//! @{ +#define EFC_ACCESS_MODE_128 0 +#define EFC_ACCESS_MODE_64 EEFC_FMR_FAM +//! @} + +uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws); +void efc_enable_frdy_interrupt(Efc *p_efc); +void efc_disable_frdy_interrupt(Efc *p_efc); +void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode); +uint32_t efc_get_flash_access_mode(Efc *p_efc); +void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws); +uint32_t efc_get_wait_state(Efc *p_efc); +uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command, + uint32_t ul_argument); +uint32_t efc_get_status(Efc *p_efc); +uint32_t efc_get_result(Efc *p_efc); +uint32_t efc_perform_read_sequence(Efc *p_efc, + uint32_t ul_cmd_st, uint32_t ul_cmd_sp, + uint32_t *p_ul_buf, uint32_t ul_size); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* EFC_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/matrix/matrix.c b/SAM3S4B/src/ASF/drivers1/matrix/matrix.c new file mode 100644 index 0000000..9816d95 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/matrix/matrix.c @@ -0,0 +1,395 @@ +/** + * \file + * + * \brief Matrix driver for SAM. + * + * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "matrix.h" + +/* / @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* / @endcond */ + +/** + * \defgroup sam_drivers_matrix_group Matrix (MATRIX) + * + * \par Purpose + * + * The Bus Matrix implements a multi-layer AHB that enables parallel access + * paths between multiple AHB masters and slaves in a system, which increases + * the overall bandwidth. + * + * @{ + */ + +/** + * \brief Set undefined length burst type of the specified master. + * + * \param ul_id Master index. + * \param burst_type Undefined length burst type. + */ +void matrix_set_master_burst_type(uint32_t ul_id, burst_type_t burst_type) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_MCFG[ul_id] & (~MATRIX_MCFG_ULBT_Msk); + p_matrix->MATRIX_MCFG[ul_id] = ul_reg | (uint32_t)burst_type; +} + +/** + * \brief Get undefined length burst type of the specified master. + * + * \param ul_id Master index. + * + * \return Undefined length burst type. + */ +burst_type_t matrix_get_master_burst_type(uint32_t ul_id) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_MCFG[ul_id] & (MATRIX_MCFG_ULBT_Msk); + return (burst_type_t)ul_reg; +} + +/** + * \brief Set slot cycle of the specified slave. + * + * \param ul_id Slave index. + * \param ul_slot_cycle Number of slot cycle. + */ +void matrix_set_slave_slot_cycle(uint32_t ul_id, uint32_t ul_slot_cycle) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (~MATRIX_SCFG_SLOT_CYCLE_Msk); + p_matrix->MATRIX_SCFG[ul_id] = ul_reg | MATRIX_SCFG_SLOT_CYCLE( + ul_slot_cycle); +} + +/** + * \brief Get slot cycle of the specified slave. + * + * \param ul_id Slave index. + * + * \return Number of slot cycle. + */ +uint32_t matrix_get_slave_slot_cycle(uint32_t ul_id) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_SLOT_CYCLE_Msk); + return (ul_reg >> MATRIX_SCFG_SLOT_CYCLE_Pos); +} + +/** + * \brief Set default master type of the specified slave. + * + * \param ul_id Slave index. + * \param type Default master type. + */ +void matrix_set_slave_default_master_type(uint32_t ul_id, defaut_master_t type) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (~MATRIX_SCFG_DEFMSTR_TYPE_Msk); + p_matrix->MATRIX_SCFG[ul_id] = ul_reg | (uint32_t)type; +} + +/** + * \brief Get default master type of the specified slave. + * + * \param ul_id Slave index. + * + * \return Default master type. + */ +defaut_master_t matrix_get_slave_default_master_type(uint32_t ul_id) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_DEFMSTR_TYPE_Msk); + return (defaut_master_t)ul_reg; +} + +/** + * \brief Set fixed default master of the specified slave. + * + * \param ul_id Slave index. + * \param ul_fixed_id Fixed default master index. + */ +void matrix_set_slave_fixed_default_master(uint32_t ul_id, uint32_t ul_fixed_id) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_SCFG[ul_id] & + (~MATRIX_SCFG_FIXED_DEFMSTR_Msk); + p_matrix->MATRIX_SCFG[ul_id] + = ul_reg | MATRIX_SCFG_FIXED_DEFMSTR(ul_fixed_id); +} + +/** + * \brief Get fixed default master of the specified slave. + * + * \param ul_id Slave index. + * + * \return Fixed default master index. + */ +uint32_t matrix_get_slave_fixed_default_master(uint32_t ul_id) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_FIXED_DEFMSTR_Msk); + return (ul_reg >> MATRIX_SCFG_FIXED_DEFMSTR_Pos); +} + +#if !SAM4E + +/** + * \brief Set slave arbitration type of the specified slave. + * + * \param ul_id Slave index. + * \param type Arbitration type. + */ +void matrix_set_slave_arbitration_type(uint32_t ul_id, arbitration_type_t type) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (~MATRIX_SCFG_ARBT_Msk); + p_matrix->MATRIX_SCFG[ul_id] = ul_reg | (uint32_t)type; +} + +/** + * \brief Get slave arbitration type of the specified slave. + * + * \param ul_id Slave index. + * + * \return Arbitration type. + */ +arbitration_type_t matrix_get_slave_arbitration_type(uint32_t ul_id) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t ul_reg; + + ul_reg = p_matrix->MATRIX_SCFG[ul_id] & (MATRIX_SCFG_ARBT_Msk); + return (arbitration_type_t)ul_reg; +} + +#endif + +/** + * \brief Set priority for the specified slave access. + * + * \param ul_id Slave index. + * \param ul_prio Bitmask OR of priorities of master x. + */ +void matrix_set_slave_priority(uint32_t ul_id, uint32_t ul_prio) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t *p_PRAS; + uint32_t ul_dlt; + + ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRAS1); + ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRAS0); + + p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRAS0) + + ul_id * ul_dlt); + + *p_PRAS = ul_prio; +} + +/** + * \brief Get priority for the specified slave access. + * + * \param ul_id Slave index. + * + * \return Bitmask OR of priorities of master x. + */ +uint32_t matrix_get_slave_priority(uint32_t ul_id) +{ + Matrix *p_matrix = MATRIX; + volatile uint32_t *p_PRAS; + uint32_t ul_dlt; + + ul_dlt = (uint32_t)&(p_matrix->MATRIX_PRAS1); + ul_dlt = ul_dlt - (uint32_t)&(p_matrix->MATRIX_PRAS0); + + p_PRAS = (volatile uint32_t *)((uint32_t)&(p_matrix->MATRIX_PRAS0) + + ul_id * ul_dlt); + + return (*p_PRAS); +} + +#if (SAM3XA || SAM3U || SAM4E) + +/** + * \brief Set bus matrix master remap. + * + * \param ul_remap Bitmask OR of RCBx: 0 for disable, 1 for enable. + */ +void matrix_set_master_remap(uint32_t ul_remap) +{ + Matrix *p_matrix = MATRIX; + + p_matrix->MATRIX_MRCR = ul_remap; +} + +/** + * \brief Get bus matrix master remap. + * + * \return Bitmask OR of RCBx: 0 for disable, 1 for enable. + */ +uint32_t matrix_get_master_remap(void) +{ + Matrix *p_matrix = MATRIX; + + return (p_matrix->MATRIX_MRCR); +} + +#endif /* (SAM3XA || SAM3U || SAM4E) */ + +#if (SAM3S || SAM3XA || SAM3N || SAM4S || SAM4E || SAM4N) + +/** + * \brief Set system IO. + * + * \param ul_io Bitmask OR of SYSIOx. + */ +void matrix_set_system_io(uint32_t ul_io) +{ + Matrix *p_matrix = MATRIX; + + p_matrix->CCFG_SYSIO = ul_io; +} + +/** + * \brief Get system IO. + * + * \return Bitmask OR of SYSIOx. + */ +uint32_t matrix_get_system_io(void) +{ + Matrix *p_matrix = MATRIX; + + return (p_matrix->CCFG_SYSIO); +} + +#endif /* (SAM3S || SAM3XA || SAM3N || SAM4S || SAM4E) */ + +#if (SAM3S || SAM4S || SAM4E) + +/** + * \brief Set NAND Flash Chip Select configuration register. + * + * \param ul_cs Bitmask OR of SMC_NFCSx: 0 if NCSx is not assigned, + * 1 if NCSx is assigned. + */ +void matrix_set_nandflash_cs(uint32_t ul_cs) +{ + Matrix *p_matrix = MATRIX; + + p_matrix->CCFG_SMCNFCS = ul_cs; +} + +/** + * \brief Get NAND Flash Chip Select configuration register. + * + * \return Bitmask OR of SMC_NFCSx. + */ +uint32_t matrix_get_nandflash_cs(void) +{ + Matrix *p_matrix = MATRIX; + + return (p_matrix->CCFG_SMCNFCS); +} + +#endif /* (SAM3S || SAM4S || SAM4E) */ + +#define MATRIX_WPKEY 0x4D4154u /* Write Protect KEY */ + +/** + * \brief Enable or disable write protect of MATRIX registers. + * + * \param ul_enable 1 to enable, 0 to disable. + */ +void matrix_set_writeprotect(uint32_t ul_enable) +{ + Matrix *p_matrix = MATRIX; + + if (ul_enable) { + p_matrix->MATRIX_WPMR = MATRIX_WPMR_WPKEY(MATRIX_WPKEY) | + MATRIX_WPMR_WPEN; + } else { + p_matrix->MATRIX_WPMR = MATRIX_WPMR_WPKEY(MATRIX_WPKEY); + } +} + +/** + * \brief Get write protect status. + * + * \return Write protect status. + */ +uint32_t matrix_get_writeprotect_status(void) +{ + Matrix *p_matrix = MATRIX; + + return (p_matrix->MATRIX_WPSR); +} + +/* @} */ + +/* / @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* / @endcond */ diff --git a/SAM3S4B/src/ASF/drivers1/matrix/matrix.h b/SAM3S4B/src/ASF/drivers1/matrix/matrix.h new file mode 100644 index 0000000..5c2c35b --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/matrix/matrix.h @@ -0,0 +1,128 @@ +/** + * \file + * + * \brief Matrix driver for SAM. + * + * Copyright (c) 2012-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef MATRIX_H_INCLUDED +#define MATRIX_H_INCLUDED + +#include "compiler.h" + +/* / @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* / @endcond */ + +/** \brief Matrix master: undefined length burst type */ +typedef enum { + MATRIX_ULBT_INFINITE_LENGTH_BURST = MATRIX_MCFG_ULBT(0), + MATRIX_ULBT_SINGLE_ACCESS = MATRIX_MCFG_ULBT(1), + MATRIX_ULBT_FOUR_BEAT_BURST = MATRIX_MCFG_ULBT(2), + MATRIX_ULBT_EIGHT_BEAT_BURST = MATRIX_MCFG_ULBT(3), + MATRIX_ULBT_SIXTEEN_BEAT_BURST = MATRIX_MCFG_ULBT(4) +} burst_type_t; + +/** \brief Matrix slave: default master type */ +typedef enum { + MATRIX_DEFMSTR_NO_DEFAULT_MASTER = MATRIX_SCFG_DEFMSTR_TYPE(0), + MATRIX_DEFMSTR_LAST_DEFAULT_MASTER = MATRIX_SCFG_DEFMSTR_TYPE(1), + MATRIX_DEFMSTR_FIXED_DEFAULT_MASTER = MATRIX_SCFG_DEFMSTR_TYPE(2) +} defaut_master_t; + +#if !SAM4E +/** \brief Matrix slave: arbitration type */ +typedef enum { + MATRIX_ARBT_ROUND_ROBIN = MATRIX_SCFG_ARBT(0), + MATRIX_ARBT_FIXED_PRIORITY = MATRIX_SCFG_ARBT(1) +} arbitration_type_t; +#endif + +void matrix_set_master_burst_type(uint32_t ul_id, burst_type_t burst_type); +burst_type_t matrix_get_master_burst_type(uint32_t ul_id); +void matrix_set_slave_slot_cycle(uint32_t ul_id, uint32_t ul_slot_cycle); +uint32_t matrix_get_slave_slot_cycle(uint32_t ul_id); +void matrix_set_slave_default_master_type(uint32_t ul_id, defaut_master_t type); +defaut_master_t matrix_get_slave_default_master_type(uint32_t ul_id); +void matrix_set_slave_fixed_default_master(uint32_t ul_id, + uint32_t ul_fixed_id); +uint32_t matrix_get_slave_fixed_default_master(uint32_t ul_id); + +#if !SAM4E +void matrix_set_slave_arbitration_type(uint32_t ul_id, arbitration_type_t type); +arbitration_type_t matrix_get_slave_arbitration_type(uint32_t ul_id); +#endif + +void matrix_set_slave_priority(uint32_t ul_id, uint32_t ul_prio); +uint32_t matrix_get_slave_priority(uint32_t ul_id); + +#if (SAM3XA || SAM3U || SAM4E) +void matrix_set_master_remap(uint32_t ul_remap); +uint32_t matrix_get_master_remap(void); + +#endif /* (SAM3XA || SAM3U || SAM4E) */ + +#if (SAM3S || SAM3XA || SAM3N || SAM4S || SAM4E || SAM4N) +void matrix_set_system_io(uint32_t ul_io); +uint32_t matrix_get_system_io(void); + +#endif /* (SAM3S || SAM3XA || SAM3N || SAM4S || SAM4E || SAM4N) */ + +#if (SAM3S || SAM4S || SAM4E) +void matrix_set_nandflash_cs(uint32_t ul_cs); +uint32_t matrix_get_nandflash_cs(void); + +#endif /* (SAM3S || SAM4S || SAM4E) */ + +void matrix_set_writeprotect(uint32_t ul_enable); +uint32_t matrix_get_writeprotect_status(void); + +/* / @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* / @endcond */ + +#endif /* MATRIX_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/pdc/pdc.c b/SAM3S4B/src/ASF/drivers1/pdc/pdc.c new file mode 100644 index 0000000..e67a177 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pdc/pdc.c @@ -0,0 +1,266 @@ +/** + * \file + * + * \brief Peripheral DMA Controller (PDC) driver for SAM. + * + * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "pdc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_pdc_group Peripheral DMA Controller (PDC) + * + * \par Purpose + * + * The Peripheral DMA Controller (PDC) transfers data between on-chip serial + * peripherals and the on- and/or off-chip memories. The link between the PDC + * and a serial peripheral is operated by the AHB to ABP bridge. + * + * @{ + */ + +/** + * \brief Configure PDC for data transmit. + * + * \param p_pdc Pointer to a PDC instance. + * \param p_packet Pointer to packet information for current buffer register + * set, NULL to let them as is. + * \param p_next_packet Pointer to packet information for next buffer register + * set, NULL to let them as is. + */ +void pdc_tx_init(Pdc *p_pdc, pdc_packet_t *p_packet, + pdc_packet_t *p_next_packet) +{ + if (p_packet) { + p_pdc->PERIPH_TPR = p_packet->ul_addr; + p_pdc->PERIPH_TCR = p_packet->ul_size; + } + if (p_next_packet) { + p_pdc->PERIPH_TNPR = p_next_packet->ul_addr; + p_pdc->PERIPH_TNCR = p_next_packet->ul_size; + } +} + +/** + * \brief Configure PDC for data receive. + * + * \param p_pdc Pointer to a PDC instance. + * \param p_packet Pointer to packet information for current buffer register + * set, NULL to let them as is. + * \param p_next_packet Pointer to packet information for next buffer register + * set, NULL to let them as is. + */ +void pdc_rx_init(Pdc *p_pdc, pdc_packet_t *p_packet, + pdc_packet_t *p_next_packet) +{ + if (p_packet) { + p_pdc->PERIPH_RPR = p_packet->ul_addr; + p_pdc->PERIPH_RCR = p_packet->ul_size; + } + if (p_next_packet) { + p_pdc->PERIPH_RNPR = p_next_packet->ul_addr; + p_pdc->PERIPH_RNCR = p_next_packet->ul_size; + } +} + +/** + * \brief Clear PDC buffer receive counter. + * + * \param p_pdc Pointer to a PDC instance. + */ +void pdc_rx_clear_cnt(Pdc *p_pdc) +{ + p_pdc->PERIPH_RNCR = 0; + p_pdc->PERIPH_RCR = 0; +} + +/** + * \brief Enable PDC transfers (TX and/or RX). + * + * \note It is forbidden to set both TXTEN and RXTEN for a half duplex + * peripheral. + * + * \param p_pdc Pointer to a PDC instance. + * \param ul_controls Transfer directions. + * (bit PERIPH_PTCR_RXTEN and bit PERIPH_PTCR_TXTEN) + */ +void pdc_enable_transfer(Pdc *p_pdc, uint32_t ul_controls) +{ + p_pdc->PERIPH_PTCR = + ul_controls & (PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); +} + +/** + * \brief Disable PDC transfers (TX and/or RX) + * + * \param p_pdc Pointer to a PDC instance. + * \param ul_controls Transfer directions. + * (bit PERIPH_PTCR_TXTDIS, bit PERIPH_PTCR_TXTDIS) + */ +void pdc_disable_transfer(Pdc *p_pdc, uint32_t ul_controls) +{ + p_pdc->PERIPH_PTCR = + ul_controls & (PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); +} + +/** + * \brief Read PDC status. + * + * \param p_pdc Pointer to a PDC instance. + * + * \return PDC status register value. + */ +uint32_t pdc_read_status(Pdc *p_pdc) +{ + return p_pdc->PERIPH_PTSR; +} + +/** + * \brief Return Receive Pointer Register (RPR) value. + * + * \param p_pdc Pointer to a PDC instance. + * + * \return Receive Pointer Register value. + */ +uint32_t pdc_read_rx_ptr(Pdc *p_pdc) +{ + return p_pdc->PERIPH_RPR; +} + +/** + * \brief Return Receive Counter Register (RCR) value. + * + * \param p_pdc Pointer to a PDC instance. + * + * \return Receive Counter Register value. + */ +uint32_t pdc_read_rx_counter(Pdc *p_pdc) +{ + return p_pdc->PERIPH_RCR; +} + +/** + * \brief Return Transmit Pointer Register (TPR) value. + * + * \param p_pdc Pointer to a PDC instance. + * + * \return Transmit Pointer Register value. + */ +uint32_t pdc_read_tx_ptr(Pdc *p_pdc) +{ + return p_pdc->PERIPH_TPR; +} + +/** + * \brief Return Transmit Counter Register (TCR) value. + * + * \param p_pdc Pointer to a PDC instance. + * + * \return Transmit Counter Register value. + */ +uint32_t pdc_read_tx_counter(Pdc *p_pdc) +{ + return p_pdc->PERIPH_TCR; +} + +/** + * \brief Return Receive Next Pointer Register (RNPR) value. + * + * \param p_pdc Pointer to a PDC instance. + * + * \return Receive Next Pointer Register value. + */ +uint32_t pdc_read_rx_next_ptr(Pdc *p_pdc) +{ + return p_pdc->PERIPH_RNPR; +} + +/** + * \brief Return Receive Next Counter Register (RNCR) value. + * + * \param p_pdc Pointer to a PDC instance. + * + * \return Receive Next Counter Register value. + */ +uint32_t pdc_read_rx_next_counter(Pdc *p_pdc) +{ + return p_pdc->PERIPH_RNCR; +} + +/** + * \brief Return Transmit Next Pointer Register (TNPR) value. + * + * \param p_pdc Pointer to a PDC instance. + * + * \return Transmit Next Pointer Register value. + */ +uint32_t pdc_read_tx_next_ptr(Pdc *p_pdc) +{ + return p_pdc->PERIPH_TNPR; +} + +/** + * \brief Return Transmit Next Counter Register (TNCR) value. + * + * \param p_pdc Pointer to a PDC instance. + * + * \return Transmit Next Counter Register value. + */ +uint32_t pdc_read_tx_next_counter(Pdc *p_pdc) +{ + return p_pdc->PERIPH_TNCR; +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/SAM3S4B/src/ASF/drivers1/pdc/pdc.h b/SAM3S4B/src/ASF/drivers1/pdc/pdc.h new file mode 100644 index 0000000..2844ae5 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pdc/pdc.h @@ -0,0 +1,101 @@ +/** + * \file + * + * \brief Peripheral DMA Controller (PDC) driver for SAM. + * + * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef PDC_H_INCLUDED +#define PDC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/*! \brief PDC data packet for transfer */ +typedef struct pdc_packet { + /** \brief Address for PDC transfer packet. + * The pointer to packet data start address. For pointer or next pointer + * register (_PR). + */ + uint32_t ul_addr; + /** \brief PDC transfer packet size. + * Size for counter or next counter register (_CR). The max value is + * 0xffff. + * The unit of size is based on peripheral data width, that is, data + * width that each time the peripheral transfers. + * E.g., size of PDC for USART is in number of bytes, but size of PDC + * for 16 bit SSC is in number of 16 bit word. + */ + uint32_t ul_size; +} pdc_packet_t; + +void pdc_tx_init(Pdc *p_pdc, pdc_packet_t *p_packet, + pdc_packet_t *p_next_packet); +void pdc_rx_init(Pdc *p_pdc, pdc_packet_t *p_packet, + pdc_packet_t *p_next_packet); +void pdc_rx_clear_cnt(Pdc *p_pdc); +void pdc_enable_transfer(Pdc *p_pdc, uint32_t ul_controls); +void pdc_disable_transfer(Pdc *p_pdc, uint32_t ul_controls); +uint32_t pdc_read_status(Pdc *p_pdc); +uint32_t pdc_read_rx_ptr(Pdc *p_pdc); +uint32_t pdc_read_rx_counter(Pdc *p_pdc); +uint32_t pdc_read_tx_ptr(Pdc *p_pdc); +uint32_t pdc_read_tx_counter(Pdc *p_pdc); +uint32_t pdc_read_rx_next_ptr(Pdc *p_pdc); +uint32_t pdc_read_rx_next_counter(Pdc *p_pdc); +uint32_t pdc_read_tx_next_ptr(Pdc *p_pdc); +uint32_t pdc_read_tx_next_counter(Pdc *p_pdc); +unsigned char USART_WriteBuffer(Pdc *uart,void *buffer,unsigned int size); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* PDC_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/pio/pio.c b/SAM3S4B/src/ASF/drivers1/pio/pio.c new file mode 100644 index 0000000..55d231e --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pio/pio.c @@ -0,0 +1,1117 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) Controller driver for SAM. + * + * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "pio.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_pio_group Peripheral Parallel Input/Output (PIO) Controller + * + * \par Purpose + * + * The Parallel Input/Output Controller (PIO) manages up to 32 fully + * programmable input/output lines. Each I/O line may be dedicated as a + * general-purpose I/O or be assigned to a function of an embedded peripheral. + * This assures effective optimization of the pins of a product. + * + * @{ + */ + +#ifndef FREQ_SLOW_CLOCK_EXT +/* External slow clock frequency (hz) */ +#define FREQ_SLOW_CLOCK_EXT 32768 +#endif + +/** + * \brief Configure PIO internal pull-up. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_pull_up_enable Indicates if the pin(s) internal pull-up shall be + * configured. + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable) +{ + /* Enable the pull-up(s) if necessary */ + if (ul_pull_up_enable) { + p_pio->PIO_PUER = ul_mask; + } else { + p_pio->PIO_PUDR = ul_mask; + } +} + +/** + * \brief Configure Glitch or Debouncing filter for the specified input(s). + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_cut_off Cuts off frequency for debouncing filter. + */ +void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_cut_off) +{ +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) + /* Set Debouncing, 0 bit field no effect */ + p_pio->PIO_IFSCER = ul_mask; +#elif (SAM3XA || SAM3U) + /* Set Debouncing, 0 bit field no effect */ + p_pio->PIO_DIFSR = ul_mask; +#else +#error "Unsupported device" +#endif + + /* + * The debouncing filter can filter a pulse of less than 1/2 Period of a + * programmable Divided Slow Clock: + * Tdiv_slclk = ((DIV+1)*2).Tslow_clock + */ + p_pio->PIO_SCDR = PIO_SCDR_DIV((FREQ_SLOW_CLOCK_EXT / + (2 * (ul_cut_off))) - 1); +} + +/** + * \brief Set a high output level on all the PIOs defined in ul_mask. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will save the value if they are changed to outputs. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_SODR = ul_mask; +} + +/** + * \brief Set a low output level on all the PIOs defined in ul_mask. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will save the value if they are changed to outputs. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_clear(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_CODR = ul_mask; +} + +/** + * \brief Return 1 if one or more PIOs of the given Pin instance currently have + * a high level; otherwise returns 0. This method returns the actual value that + * is being read on the pin. To return the supposed output value of a pin, use + * pio_get_output_data_status() instead. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * + * \retval 1 at least one PIO currently has a high level. + * \retval 0 all PIOs have a low level. + */ +uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask) +{ + uint32_t ul_reg; + + if ((ul_type == PIO_OUTPUT_0) || (ul_type == PIO_OUTPUT_1)) { + ul_reg = p_pio->PIO_ODSR; + } else { + ul_reg = p_pio->PIO_PDSR; + } + + if ((ul_reg & ul_mask) == 0) { + return 0; + } else { + return 1; + } +} + +/** + * \brief Configure IO of a PIO controller as being controlled by a specific + * peripheral. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask) +{ + uint32_t ul_sr; + + /* Disable interrupts on the pin(s) */ + p_pio->PIO_IDR = ul_mask; + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) + switch (ul_type) { + case PIO_PERIPH_A: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); + break; + + case PIO_PERIPH_B: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] &= (~ul_mask & ul_sr); + break; + + case PIO_PERIPH_C: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] &= (~ul_mask & ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); + break; + + case PIO_PERIPH_D: + ul_sr = p_pio->PIO_ABCDSR[0]; + p_pio->PIO_ABCDSR[0] = (ul_mask | ul_sr); + + ul_sr = p_pio->PIO_ABCDSR[1]; + p_pio->PIO_ABCDSR[1] = (ul_mask | ul_sr); + break; + + /* Other types are invalid in this function */ + case PIO_INPUT: + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + case PIO_NOT_A_PIN: + return; + } +#elif (SAM3XA|| SAM3U) + switch (ul_type) { + case PIO_PERIPH_A: + ul_sr = p_pio->PIO_ABSR; + p_pio->PIO_ABSR &= (~ul_mask & ul_sr); + break; + + case PIO_PERIPH_B: + ul_sr = p_pio->PIO_ABSR; + p_pio->PIO_ABSR = (ul_mask | ul_sr); + break; + + // other types are invalid in this function + case PIO_INPUT: + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + case PIO_NOT_A_PIN: + return; + } +#else +#error "Unsupported device" +#endif + + /* Remove the pins from under the control of PIO */ + p_pio->PIO_PDR = ul_mask; +} + +/** + * \brief Configure one or more pin(s) or a PIO controller as inputs. + * Optionally, the corresponding internal pull-up(s) and glitch filter(s) can + * be enabled. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask indicating which pin(s) to configure as input(s). + * \param ul_attribute PIO attribute(s). + */ +void pio_set_input(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attribute) +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_attribute & PIO_PULLUP); + + /* Enable Input Filter if necessary */ + if (ul_attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) { + p_pio->PIO_IFER = ul_mask; + } else { + p_pio->PIO_IFDR = ul_mask; + } + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) + /* Enable de-glitch or de-bounce if necessary */ + if (ul_attribute & PIO_DEGLITCH) { + p_pio->PIO_IFSCDR = ul_mask; + } else { + if (ul_attribute & PIO_DEBOUNCE) { + p_pio->PIO_IFSCER = ul_mask; + } + } +#elif (SAM3XA|| SAM3U) + /* Enable de-glitch or de-bounce if necessary */ + if (ul_attribute & PIO_DEGLITCH) { + p_pio->PIO_SCIFSR = ul_mask; + } else { + if (ul_attribute & PIO_DEBOUNCE) { + p_pio->PIO_SCIFSR = ul_mask; + } + } +#else +#error "Unsupported device" +#endif + + /* Configure pin as input */ + p_pio->PIO_ODR = ul_mask; + p_pio->PIO_PER = ul_mask; +} + +/** + * \brief Configure one or more pin(s) of a PIO controller as outputs, with + * the given default value. Optionally, the multi-drive feature can be enabled + * on the pin(s). + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask indicating which pin(s) to configure. + * \param ul_default_level Default level on the pin(s). + * \param ul_multidrive_enable Indicates if the pin(s) shall be configured as + * open-drain. + * \param ul_pull_up_enable Indicates if the pin shall have its pull-up + * activated. + */ +void pio_set_output(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_default_level, + const uint32_t ul_multidrive_enable, + const uint32_t ul_pull_up_enable) +{ + pio_disable_interrupt(p_pio, ul_mask); + pio_pull_up(p_pio, ul_mask, ul_pull_up_enable); + + /* Enable multi-drive if necessary */ + if (ul_multidrive_enable) { + p_pio->PIO_MDER = ul_mask; + } else { + p_pio->PIO_MDDR = ul_mask; + } + + /* Set default value */ + if (ul_default_level) { + p_pio->PIO_SODR = ul_mask; + } else { + p_pio->PIO_CODR = ul_mask; + } + + /* Configure pin(s) as output(s) */ + p_pio->PIO_OER = ul_mask; + p_pio->PIO_PER = ul_mask; +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_type PIO type. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_attribute Pins attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask, const uint32_t ul_attribute) +{ + /* Configure pins */ + switch (ul_type) { + case PIO_PERIPH_A: + case PIO_PERIPH_B: +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) + case PIO_PERIPH_C: + case PIO_PERIPH_D: +#endif + pio_set_peripheral(p_pio, ul_type, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_attribute & PIO_PULLUP)); + break; + + case PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_attribute); + break; + + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, (ul_type == PIO_OUTPUT_1), + (ul_attribute & PIO_OPENDRAIN) ? 1 : 0, + (ul_attribute & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Return 1 if one or more PIOs of the given Pin are configured to + * output a high level (even if they are not output). + * To get the actual value of the pin, use PIO_Get() instead. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s). + * + * \retval 1 At least one PIO is configured to output a high level. + * \retval 0 All PIOs are configured to output a low level. + */ +uint32_t pio_get_output_data_status(const Pio *p_pio, + const uint32_t ul_mask) +{ + if ((p_pio->PIO_ODSR & ul_mask) == 0) { + return 0; + } else { + return 1; + } +} + +/** + * \brief Configure PIO pin multi-driver. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_multi_driver_enable Indicates if the pin(s) multi-driver shall be + * configured. + */ +void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_multi_driver_enable) +{ + /* Enable the multi-driver if necessary */ + if (ul_multi_driver_enable) { + p_pio->PIO_MDER = ul_mask; + } else { + p_pio->PIO_MDDR = ul_mask; + } +} + +/** + * \brief Get multi-driver status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The multi-driver mask value. + */ +uint32_t pio_get_multi_driver_status(const Pio *p_pio) +{ + return p_pio->PIO_MDSR; +} + + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) +/** + * \brief Configure PIO pin internal pull-down. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_pull_down_enable Indicates if the pin(s) internal pull-down shall + * be configured. + */ +void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_down_enable) +{ + /* Enable the pull-down if necessary */ + if (ul_pull_down_enable) { + p_pio->PIO_PPDER = ul_mask; + } else { + p_pio->PIO_PPDDR = ul_mask; + } +} +#endif + +/** + * \brief Enable PIO output write for synchronous data output. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_OWER = ul_mask; +} + +/** + * \brief Disable PIO output write. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_OWDR = ul_mask; +} + +/** + * \brief Read PIO output write status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The output write mask value. + */ +uint32_t pio_get_output_write_status(const Pio *p_pio) +{ + return p_pio->PIO_OWSR; +} + +/** + * \brief Synchronously write on output pins. + * \note Only bits unmasked by PIO_OWSR (Output Write Status Register) are + * written. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_ODSR = ul_mask; +} + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) +/** + * \brief Configure PIO pin schmitt trigger. By default the Schmitt trigger is + * active. + * Disabling the Schmitt Trigger is requested when using the QTouch Library. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_SCHMITT = ul_mask; +} + +/** + * \brief Get PIO pin schmitt trigger status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The schmitt trigger mask value. + */ +uint32_t pio_get_schmitt_trigger(const Pio *p_pio) +{ + return p_pio->PIO_SCHMITT; +} +#endif + +/** + * \brief Configure the given interrupt source. + * Interrupt can be configured to trigger on rising edge, falling edge, + * high level, low level or simply on level change. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt source bit map. + * \param ul_attr Interrupt source attributes. + */ +void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attr) +{ + /* Configure additional interrupt mode registers. */ + if (ul_attr & PIO_IT_AIME) { + /* Enable additional interrupt mode. */ + p_pio->PIO_AIMER = ul_mask; + + /* If bit field of the selected pin is 1, set as + Rising Edge/High level detection event. */ + if (ul_attr & PIO_IT_RE_OR_HL) { + /* Rising Edge or High Level */ + p_pio->PIO_REHLSR = ul_mask; + } else { + /* Falling Edge or Low Level */ + p_pio->PIO_FELLSR = ul_mask; + } + + /* If bit field of the selected pin is 1, set as + edge detection source. */ + if (ul_attr & PIO_IT_EDGE) { + /* Edge select */ + p_pio->PIO_ESR = ul_mask; + } else { + /* Level select */ + p_pio->PIO_LSR = ul_mask; + } + } else { + /* Disable additional interrupt mode. */ + p_pio->PIO_AIMDR = ul_mask; + } +} + +/** + * \brief Enable the given interrupt source. + * The PIO must be configured as an NVIC interrupt source as well. + * The status register of the corresponding PIO controller is cleared + * prior to enabling the interrupt. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_ISR; + p_pio->PIO_IER = ul_mask; +} + +/** + * \brief Disable a given interrupt source, with no added side effects. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_IDR = ul_mask; +} + +/** + * \brief Read PIO interrupt status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt status mask value. + */ +uint32_t pio_get_interrupt_status(const Pio *p_pio) +{ + return p_pio->PIO_ISR; +} + +/** + * \brief Read PIO interrupt mask. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt mask value. + */ +uint32_t pio_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_IMR; +} + +/** + * \brief Set additional interrupt mode. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + * \param ul_attribute Pin(s) attributes. + */ +void pio_set_additional_interrupt_mode(Pio *p_pio, + const uint32_t ul_mask, const uint32_t ul_attribute) +{ + /* Enables additional interrupt mode if needed */ + if (ul_attribute & PIO_IT_AIME) { + /* Enables additional interrupt mode */ + p_pio->PIO_AIMER = ul_mask; + + /* Configures the Polarity of the event detection */ + /* (Rising/Falling Edge or High/Low Level) */ + if (ul_attribute & PIO_IT_RE_OR_HL) { + /* Rising Edge or High Level */ + p_pio->PIO_REHLSR = ul_mask; + } else { + /* Falling Edge or Low Level */ + p_pio->PIO_FELLSR = ul_mask; + } + + /* Configures the type of event detection (Edge or Level) */ + if (ul_attribute & PIO_IT_EDGE) { + /* Edge select */ + p_pio->PIO_ESR = ul_mask; + } else { + /* Level select */ + p_pio->PIO_LSR = ul_mask; + } + } else { + /* Disable additional interrupt mode */ + p_pio->PIO_AIMDR = ul_mask; + } +} + +#define PIO_WPMR_WPKEY_VALUE PIO_WPMR_WPKEY(0x50494Fu) + +/** + * \brief Enable or disable write protect of PIO registers. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_enable 1 to enable, 0 to disable. + */ +void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable) +{ + p_pio->PIO_WPMR = PIO_WPMR_WPKEY_VALUE | ul_enable; +} + +/** + * \brief Read write protect status. + * + * \param p_pio Pointer to a PIO instance. + * + * \return Return write protect status. + */ +uint32_t pio_get_writeprotect_status(const Pio *p_pio) +{ + return p_pio->PIO_WPSR; +} + +/** + * \brief Return the value of a pin. + * + * \param ul_pin The pin number. + * + * \return The pin value. + * + * \note If pin is output: a pull-up or pull-down could hide the actual value. + * The function \ref pio_get can be called to get the actual pin output + * level. + * \note If pin is input: PIOx must be clocked to sample the signal. + * See PMC driver. + */ +uint32_t pio_get_pin_value(uint32_t ul_pin) +{ + Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + return (p_pio->PIO_PDSR >> (ul_pin & 0x1F)) & 1; +} + +/** + * \brief Drive a GPIO pin to 1. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called beforehand. + */ +void pio_set_pin_high(uint32_t ul_pin) +{ + Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); +} + +/** + * \brief Drive a GPIO pin to 0. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called before. + */ +void pio_set_pin_low(uint32_t ul_pin) +{ + Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); +} + +/** + * \brief Toggle a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref pio_configure_pin must be called before. + */ +void pio_toggle_pin(uint32_t ul_pin) +{ + Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + if (p_pio->PIO_ODSR & (1 << (ul_pin & 0x1F))) { + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = 1 << (ul_pin & 0x1F); + } else { + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = 1 << (ul_pin & 0x1F); + } +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param ul_pin Bitmask of one or more pin(s) to configure. + * \param ul_flags Pins attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags) +{ + Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) + case PIO_TYPE_PIO_PERIPH_C: + pio_set_peripheral(p_pio, PIO_PERIPH_C, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_D: + pio_set_peripheral(p_pio, PIO_PERIPH_D, (1 << (ul_pin & 0x1F))); + pio_pull_up(p_pio, (1 << (ul_pin & 0x1F)), + (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, (1 << (ul_pin & 0x1F)), ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, (1 << (ul_pin & 0x1F)), + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Drive a GPIO port to 1. + * + * \param p_pio Base address of the PIO port. + * \param ul_mask Bitmask of one or more pin(s) to toggle. + */ +void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask) +{ + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = ul_mask; +} + +/** + * \brief Drive a GPIO port to 0. + * + * \param p_pio Base address of the PIO port. + * \param ul_mask Bitmask of one or more pin(s) to toggle. + */ +void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask) +{ + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = ul_mask; +} + +/** + * \brief Toggle a GPIO group. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + */ +void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask) +{ + if (p_pio->PIO_ODSR & ul_mask) { + /* Value to be driven on the I/O line: 0. */ + p_pio->PIO_CODR = ul_mask; + } else { + /* Value to be driven on the I/O line: 1. */ + p_pio->PIO_SODR = ul_mask; + } +} + +/** + * \brief Perform complete pin(s) configuration; general attributes and PIO init + * if necessary. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Bitmask of one or more pin(s) to configure. + * \param ul_flags Pin(s) attributes. + * + * \return Whether the pin(s) have been configured properly. + */ +uint32_t pio_configure_pin_group(Pio *p_pio, + uint32_t ul_mask, const uint32_t ul_flags) +{ + /* Configure pins */ + switch (ul_flags & PIO_TYPE_Msk) { + case PIO_TYPE_PIO_PERIPH_A: + pio_set_peripheral(p_pio, PIO_PERIPH_A, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_B: + pio_set_peripheral(p_pio, PIO_PERIPH_B, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) + case PIO_TYPE_PIO_PERIPH_C: + pio_set_peripheral(p_pio, PIO_PERIPH_C, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; + case PIO_TYPE_PIO_PERIPH_D: + pio_set_peripheral(p_pio, PIO_PERIPH_D, ul_mask); + pio_pull_up(p_pio, ul_mask, (ul_flags & PIO_PULLUP)); + break; +#endif + + case PIO_TYPE_PIO_INPUT: + pio_set_input(p_pio, ul_mask, ul_flags); + break; + + case PIO_TYPE_PIO_OUTPUT_0: + case PIO_TYPE_PIO_OUTPUT_1: + pio_set_output(p_pio, ul_mask, + ((ul_flags & PIO_TYPE_PIO_OUTPUT_1) + == PIO_TYPE_PIO_OUTPUT_1) ? 1 : 0, + (ul_flags & PIO_OPENDRAIN) ? 1 : 0, + (ul_flags & PIO_PULLUP) ? 1 : 0); + break; + + default: + return 0; + } + + return 1; +} + +/** + * \brief Enable interrupt for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +void pio_enable_pin_interrupt(uint32_t ul_pin) +{ + Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + p_pio->PIO_IER = 1 << (ul_pin & 0x1F); +} + + +/** + * \brief Disable interrupt for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \note The function \ref gpio_configure_pin must be called before. + */ +void pio_disable_pin_interrupt(uint32_t ul_pin) +{ + Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + p_pio->PIO_IDR = 1 << (ul_pin & 0x1F); +} + + +/** + * \brief Return GPIO port for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return Pointer to \ref Pio struct for GPIO port. + */ +Pio *pio_get_pin_group(uint32_t ul_pin) +{ + Pio *p_pio = (Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))); + return p_pio; +} + +/** + * \brief Return GPIO port peripheral ID for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return GPIO port peripheral ID. + */ +uint32_t pio_get_pin_group_id(uint32_t ul_pin) +{ + uint32_t ul_id = ID_PIOA + (ul_pin >> 5); + return ul_id; +} + + +/** + * \brief Return GPIO port pin mask for a GPIO pin. + * + * \param ul_pin The pin index. + * + * \return GPIO port pin mask. + */ +uint32_t pio_get_pin_group_mask(uint32_t ul_pin) +{ + uint32_t ul_mask = 1 << (ul_pin & 0x1F); + return ul_mask; +} + +#if (SAM3S || SAM4S || SAM4E) +/* Capture mode enable flag */ +uint32_t pio_capture_enable_flag; + +/** + * \brief Configure PIO capture mode. + * \note PIO capture mode will be disabled automatically. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mode Bitmask of one or more modes. + */ +void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode) +{ + ul_mode &= (~PIO_PCMR_PCEN); /* Disable PIO capture mode */ + p_pio->PIO_PCMR = ul_mode; +} + +/** + * \brief Enable PIO capture mode. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_capture_enable(Pio *p_pio) +{ + p_pio->PIO_PCMR |= PIO_PCMR_PCEN; + pio_capture_enable_flag = true; +} + +/** + * \brief Disable PIO capture mode. + * + * \param p_pio Pointer to a PIO instance. + */ +void pio_capture_disable(Pio *p_pio) +{ + p_pio->PIO_PCMR &= (~PIO_PCMR_PCEN); + pio_capture_enable_flag = false; +} + +/** + * \brief Read from Capture Reception Holding Register. + * \note Data presence should be tested before any read attempt. + * + * \param p_pio Pointer to a PIO instance. + * \param pul_data Pointer to store the data. + * + * \retval 0 Success. + * \retval 1 I/O Failure, Capture data is not ready. + */ +uint32_t pio_capture_read(const Pio *p_pio, uint32_t *pul_data) +{ + /* Check if the data is ready */ + if ((p_pio->PIO_PCISR & PIO_PCISR_DRDY) == 0) { + return 1; + } + + /* Read data */ + *pul_data = p_pio->PIO_PCRHR; + return 0; +} + +/** + * \brief Enable the given interrupt source of PIO capture. The status + * register of the corresponding PIO capture controller is cleared prior + * to enabling the interrupt. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_PCISR; + p_pio->PIO_PCIER = ul_mask; +} + +/** + * \brief Disable a given interrupt source of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * \param ul_mask Interrupt sources bit map. + */ +void pio_capture_disable_interrupt(Pio *p_pio, const uint32_t ul_mask) +{ + p_pio->PIO_PCIDR = ul_mask; +} + +/** + * \brief Read PIO interrupt status of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt status mask value. + */ +uint32_t pio_capture_get_interrupt_status(const Pio *p_pio) +{ + return p_pio->PIO_PCISR; +} + +/** + * \brief Read PIO interrupt mask of PIO capture. + * + * \param p_pio Pointer to a PIO instance. + * + * \return The interrupt mask value. + */ +uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio) +{ + return p_pio->PIO_PCIMR; +} + +/** + * \brief Get PDC registers base address. + * + * \param p_pio Pointer to an PIO peripheral. + * + * \return PIOA PDC register base address. + */ +Pdc *pio_capture_get_pdc_base(const Pio *p_pio) +{ + UNUSED(p_pio); /* Stop warning */ + return PDC_PIOA; +} +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/SAM3S4B/src/ASF/drivers1/pio/pio.h b/SAM3S4B/src/ASF/drivers1/pio/pio.h new file mode 100644 index 0000000..e60768f --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pio/pio.h @@ -0,0 +1,340 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) Controller driver for SAM. + * + * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef PIO_H_INCLUDED +#define PIO_H_INCLUDED + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Compute PIO register length */ +#define PIO_DELTA ((uint32_t) PIOB - (uint32_t) PIOA) + +/* GPIO Support */ +#define PIO_TYPE_Pos 27 +/* PIO Type Mask */ +#define PIO_TYPE_Msk (0xFu << PIO_TYPE_Pos) +/* The pin is not a function pin. */ +#define PIO_TYPE_NOT_A_PIN (0x0u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral A. */ +#define PIO_TYPE_PIO_PERIPH_A (0x1u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral B. */ +#define PIO_TYPE_PIO_PERIPH_B (0x2u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral C. */ +#define PIO_TYPE_PIO_PERIPH_C (0x3u << PIO_TYPE_Pos) +/* The pin is controlled by the peripheral D. */ +#define PIO_TYPE_PIO_PERIPH_D (0x4u << PIO_TYPE_Pos) +/* The pin is an input. */ +#define PIO_TYPE_PIO_INPUT (0x5u << PIO_TYPE_Pos) +/* The pin is an output and has a default level of 0. */ +#define PIO_TYPE_PIO_OUTPUT_0 (0x6u << PIO_TYPE_Pos) +/* The pin is an output and has a default level of 1. */ +#define PIO_TYPE_PIO_OUTPUT_1 (0x7u << PIO_TYPE_Pos) + +typedef enum _pio_type { + PIO_NOT_A_PIN = PIO_TYPE_NOT_A_PIN, + PIO_PERIPH_A = PIO_TYPE_PIO_PERIPH_A, + PIO_PERIPH_B = PIO_TYPE_PIO_PERIPH_B, +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) + PIO_PERIPH_C = PIO_TYPE_PIO_PERIPH_C, + PIO_PERIPH_D = PIO_TYPE_PIO_PERIPH_D, +#endif + PIO_INPUT = PIO_TYPE_PIO_INPUT, + PIO_OUTPUT_0 = PIO_TYPE_PIO_OUTPUT_0, + PIO_OUTPUT_1 = PIO_TYPE_PIO_OUTPUT_1 +} pio_type_t; + +/* Default pin configuration (no attribute). */ +#define PIO_DEFAULT (0u << 0) +/* The internal pin pull-up is active. */ +#define PIO_PULLUP (1u << 0) +/* The internal glitch filter is active. */ +#define PIO_DEGLITCH (1u << 1) +/* The pin is open-drain. */ +#define PIO_OPENDRAIN (1u << 2) + +/* The internal debouncing filter is active. */ +#define PIO_DEBOUNCE (1u << 3) + +/* Enable additional interrupt modes. */ +#define PIO_IT_AIME (1u << 4) + +/* Interrupt High Level/Rising Edge detection is active. */ +#define PIO_IT_RE_OR_HL (1u << 5) +/* Interrupt Edge detection is active. */ +#define PIO_IT_EDGE (1u << 6) + +/* Low level interrupt is active */ +#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) +/* High level interrupt is active */ +#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) +/* Falling edge interrupt is active */ +#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) +/* Rising edge interrupt is active */ +#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) + +/* + * The #attribute# field is a bitmask that can either be set to PIO_DEFAULT, + * or combine (using bitwise OR '|') any number of the following constants: + * - PIO_PULLUP + * - PIO_DEGLITCH + * - PIO_DEBOUNCE + * - PIO_OPENDRAIN + * - PIO_IT_LOW_LEVEL + * - PIO_IT_HIGH_LEVEL + * - PIO_IT_FALL_EDGE + * - PIO_IT_RISE_EDGE + */ +void pio_pull_up(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_up_enable); +void pio_set_debounce_filter(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_cut_off); +void pio_set(Pio *p_pio, const uint32_t ul_mask); +void pio_clear(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask); +void pio_set_peripheral(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask); +void pio_set_input(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attribute); +void pio_set_output(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_default_level, + const uint32_t ul_multidrive_enable, + const uint32_t ul_pull_up_enable); +uint32_t pio_configure(Pio *p_pio, const pio_type_t ul_type, + const uint32_t ul_mask, const uint32_t ul_attribute); +uint32_t pio_get_output_data_status(const Pio *p_pio, + const uint32_t ul_mask); +void pio_set_multi_driver(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_multi_driver_enable); +uint32_t pio_get_multi_driver_status(const Pio *p_pio); + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) +void pio_pull_down(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_pull_down_enable); +#endif + +void pio_enable_output_write(Pio *p_pio, const uint32_t ul_mask); +void pio_disable_output_write(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_output_write_status(const Pio *p_pio); +void pio_sync_output_write(Pio *p_pio, const uint32_t ul_mask); + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) +void pio_set_schmitt_trigger(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_schmitt_trigger(const Pio *p_pio); +#endif + +void pio_configure_interrupt(Pio *p_pio, const uint32_t ul_mask, + const uint32_t ul_attr); +void pio_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); +void pio_disable_interrupt(Pio *p_pio, const uint32_t ul_mask); +uint32_t pio_get_interrupt_status(const Pio *p_pio); +uint32_t pio_get_interrupt_mask(const Pio *p_pio); +void pio_set_additional_interrupt_mode(Pio *p_pio, + const uint32_t ul_mask, const uint32_t ul_attribute); +void pio_set_writeprotect(Pio *p_pio, const uint32_t ul_enable); +uint32_t pio_get_writeprotect_status(const Pio *p_pio); + +#if (SAM3S || SAM4S || SAM4E) +void pio_capture_set_mode(Pio *p_pio, uint32_t ul_mode); +void pio_capture_enable(Pio *p_pio); +void pio_capture_disable(Pio *p_pio); +uint32_t pio_capture_read(const Pio *p_pio, uint32_t * pul_data); +void pio_capture_enable_interrupt(Pio *p_pio, const uint32_t ul_mask); +void pio_capture_disable_interrupt(Pio * p_pio, const uint32_t ul_mask); +uint32_t pio_capture_get_interrupt_status(const Pio *p_pio); +uint32_t pio_capture_get_interrupt_mask(const Pio *p_pio); +Pdc *pio_capture_get_pdc_base(const Pio *p_pio); +#endif + +/* GPIO Support */ +uint32_t pio_get_pin_value(uint32_t pin); +void pio_set_pin_high(uint32_t pin); +void pio_set_pin_low(uint32_t pin); +void pio_toggle_pin(uint32_t pin); +void pio_enable_pin_interrupt(uint32_t pin); +void pio_disable_pin_interrupt(uint32_t pin); +Pio *pio_get_pin_group(uint32_t pin); +uint32_t pio_get_pin_group_id(uint32_t pin); +uint32_t pio_get_pin_group_mask(uint32_t pin); +uint32_t pio_configure_pin(uint32_t ul_pin, const uint32_t ul_flags); +void pio_set_pin_group_high(Pio *p_pio, uint32_t ul_mask); +void pio_set_pin_group_low(Pio *p_pio, uint32_t ul_mask); +void pio_toggle_pin_group(Pio *p_pio, uint32_t ul_mask); +uint32_t pio_configure_pin_group(Pio *p_pio, uint32_t ul_mask, + const uint32_t ul_flags); + +/** + * \page sam_pio_quickstart Quick Start Guide for the SAM PIO driver + * + * This is the quick start guide for the \ref sam_drivers_pio_group "PIO Driver", + * with step-by-step instructions on how to configure and use the driver for + * specific use cases. + * + * The section described below can be compiled into e.g. the main application + * loop or any other function that will need to interface with the IO port. + * + * \section sam_pio_usecases PIO use cases + * - \ref sam_pio_quickstart_basic + * - \ref sam_pio_quickstart_use_case_2 + * + * \section sam_pio_quickstart_basic Basic usage of the PIO driver + * This section will present a basic use case for the PIO driver. This use case + * will configure pin 23 on port A as output and pin 16 as an input with pullup, + * and then toggle the output pin's value to match that of the input pin. + * + * \subsection sam_pio_quickstart_use_case_1_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * + * \subsection sam_pio_quickstart_use_case_1_setup_steps Initialization code + * Add to the application initialization code: + * \code + * pmc_enable_periph_clk(ID_PIOA); + * + * pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); + * pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); + * \endcode + * + * \subsection sam_pio_quickstart_use_case_1_setup_steps_workflow Workflow + * -# Enable the module clock to the PIOA peripheral: + * \code pmc_enable_periph_clk(ID_PIOA); \endcode + * -# Set pin 23 direction on PIOA as output, default low level: + * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode + * -# Set pin 16 direction on PIOA as input, with pullup: + * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode + * + * \subsection sam_pio_quickstart_use_case_1_example_code Example code + * Set the state of output pin 23 to match input pin 16: + * \code + * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + * pio_clear(PIOA, PIO_PA23); + * else + * pio_set(PIOA, PIO_PA23); + * \endcode + * + * \subsection sam_pio_quickstart_use_case_1_example_workflow Workflow + * -# We check the value of the pin: + * \code + * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + * \endcode + * -# Then we set the new output value based on the read pin value: + * \code + * pio_clear(PIOA, PIO_PA23); + * else + * pio_set(PIOA, PIO_PA23); + * \endcode + */ + +/** + * \page sam_pio_quickstart_use_case_2 Advanced use case - Interrupt driven edge detection + * + * \section sam_pio_quickstart_use_case_2 Advanced Use Case 1 + * This section will present a more advanced use case for the PIO driver. This use case + * will configure pin 23 on port A as output and pin 16 as an input with pullup, + * and then toggle the output pin's value to match that of the input pin using the interrupt + * controller within the device. + * + * \subsection sam_pio_quickstart_use_case_2_prereq Prerequisites + * - \ref group_pmc "Power Management Controller driver" + * + * \subsection sam_pio_quickstart_use_case_2_setup_steps Initialization code + * Add to the application initialization code: + * \code + * pmc_enable_periph_clk(ID_PIOA); + * + * pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); + * pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); + * + * pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); + * pio_enable_interrupt(PIOA, PIO_PA16); + * + * NVIC_EnableIRQ(PIOA_IRQn); + * \endcode + * + * \subsection sam_pio_quickstart_use_case_2_setup_steps_workflow Workflow + * -# Enable the module clock to the PIOA peripheral: + * \code pmc_enable_periph_clk(ID_PIOA); \endcode + * -# Set pin 23 direction on PIOA as output, default low level: + * \code pio_set_output(PIOA, PIO_PA23, LOW, DISABLE, ENABLE); \endcode + * -# Set pin 16 direction on PIOA as input, with pullup: + * \code pio_set_input(PIOA, PIO_PA16, PIO_PULLUP); \endcode + * -# Configure the input pin 16 interrupt mode and handler: + * \code pio_handler_set(PIOA, ID_PIOA, PIO_PA16, PIO_IT_EDGE, pin_edge_handler); \endcode + * -# Enable the interrupt for the configured input pin: + * \code pio_enable_interrupt(PIOA, PIO_PA16); \endcode + * -# Enable interrupt handling from the PIOA module: + * \code NVIC_EnableIRQ(PIOA_IRQn); \endcode + * + * \subsection sam_pio_quickstart_use_case_2_example_code Example code + * Add the following function to your application: + * \code + * void pin_edge_handler(void) + * { + * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + * pio_clear(PIOA, PIO_PA23); + * else + * pio_set(PIOA, PIO_PA23); + * } + * \endcode + * + * \subsection sam_pio_quickstart_use_case_2_example_workflow Workflow + * -# We check the value of the pin: + * \code + * if (pio_get(PIOA, PIO_TYPE_PIO_INPUT, PIO_PA16)) + * \endcode + * -# Then we set the new output value based on the read pin value: + * \code + * pio_clear(PIOA, PIO_PA23); + * else + * pio_set(PIOA, PIO_PA23); + * \endcode + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PIO_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/pio/pio_handler.c b/SAM3S4B/src/ASF/drivers1/pio/pio_handler.c new file mode 100644 index 0000000..748b9a1 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pio/pio_handler.c @@ -0,0 +1,281 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) interrupt handler for SAM. + * + * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "exceptions.h" +#include "pio.h" +#include "pio_handler.h" + +/** + * Maximum number of interrupt sources that can be defined. This + * constant can be increased, but the current value is the smallest possible one + * that will be compatible with all existing projects. + */ +#define MAX_INTERRUPT_SOURCES 7 + +/** + * Describes a PIO interrupt source, including the PIO instance triggering the + * interrupt and the associated interrupt handler. + */ +struct s_interrupt_source { + uint32_t id; + uint32_t mask; + uint32_t attr; + + /* Interrupt handler. */ + void (*handler) (const uint32_t, const uint32_t); +}; + + +/* List of interrupt sources. */ +static struct s_interrupt_source gs_interrupt_sources[MAX_INTERRUPT_SOURCES]; + +/* Number of currently defined interrupt sources. */ +static uint32_t gs_ul_nb_sources = 0; + +#if (SAM3S || SAM4S || SAM4E) +/* PIO Capture handler */ +static void (*pio_capture_handler)(Pio *) = NULL; +extern uint32_t pio_capture_enable_flag; +#endif + +/** + * \brief Process an interrupt request on the given PIO controller. + * + * \param p_pio PIO controller base address. + * \param ul_id PIO controller ID. + */ +void pio_handler_process(Pio *p_pio, uint32_t ul_id) +{ + uint32_t status; + uint32_t i; + + /* Read PIO controller status */ + status = pio_get_interrupt_status(p_pio); + status &= pio_get_interrupt_mask(p_pio); + + /* Check pending events */ + if (status != 0) { + /* Find triggering source */ + i = 0; + while (status != 0) { + /* Source is configured on the same controller */ + if (gs_interrupt_sources[i].id == ul_id) { + /* Source has PIOs whose statuses have changed */ + if ((status & gs_interrupt_sources[i].mask) != 0) { + gs_interrupt_sources[i].handler(gs_interrupt_sources[i].id, + gs_interrupt_sources[i].mask); + status &= ~(gs_interrupt_sources[i].mask); + } + } + i++; + } + } + + /* Check capture events */ +#if (SAM3S || SAM4S || SAM4E) + if (pio_capture_enable_flag) { + if (pio_capture_handler) { + pio_capture_handler(p_pio); + } + } +#endif +} + +/** + * \brief Set an interrupt handler for the provided pins. + * The provided handler will be called with the triggering pin as its parameter + * as soon as an interrupt is detected. + * + * \param p_pio PIO controller base address. + * \param ul_id PIO ID. + * \param ul_mask Pins (bit mask) to configure. + * \param ul_attr Pins attribute to configure. + * \param p_handler Interrupt handler function pointer. + * + * \return 0 if successful, 1 if the maximum number of sources has been defined. + */ +uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, + uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)) +{ + struct s_interrupt_source *pSource; + + if (gs_ul_nb_sources >= MAX_INTERRUPT_SOURCES) + return 1; + + /* Define new source */ + pSource = &(gs_interrupt_sources[gs_ul_nb_sources]); + pSource->id = ul_id; + pSource->mask = ul_mask; + pSource->attr = ul_attr; + pSource->handler = p_handler; + gs_ul_nb_sources++; + + /* Configure interrupt mode */ + pio_configure_interrupt(p_pio, ul_mask, ul_attr); + + return 0; +} + +#if (SAM3S || SAM4S || SAM4E) +/** + * \brief Set a capture interrupt handler for all PIO. + * + * The handler will be called with the triggering PIO as its parameter + * as soon as an interrupt is detected. + * + * \param p_handler Interrupt handler function pointer. + * + */ +void pio_capture_handler_set(void (*p_handler)(Pio *)) +{ + pio_capture_handler = p_handler; +} +#endif + +#ifdef ID_PIOA +/** + * \brief Set an interrupt handler for the specified pin. + * The provided handler will be called with the triggering pin as its parameter + * as soon as an interrupt is detected. + * + * \param ul_pin Pin index to configure. + * \param ul_flag Pin flag. + * \param p_handler Interrupt handler function pointer. + * + * \return 0 if successful, 1 if the maximum number of sources has been defined. + */ +uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, + void (*p_handler) (uint32_t, uint32_t)) +{ + return pio_handler_set((Pio *)((uint32_t)PIOA + (PIO_DELTA * (ul_pin >> 5))), + ID_PIOA + (ul_pin >> 5), + (1 << (ul_pin & 0x1F)), + ul_flag, + p_handler); +} + +/** + * \brief Parallel IO Controller A interrupt handler. + * Redefined PIOA interrupt handler for NVIC interrupt table. + */ +void PIOA_Handler(void) +{ + pio_handler_process(PIOA, ID_PIOA); +} +#endif + +#ifdef ID_PIOB +/** + * \brief Parallel IO Controller B interrupt handler + * Redefined PIOB interrupt handler for NVIC interrupt table. + */ +void PIOB_Handler(void) +{ + pio_handler_process(PIOB, ID_PIOB); +} +#endif + +#ifdef ID_PIOC +/** + * \brief Parallel IO Controller C interrupt handler. + * Redefined PIOC interrupt handler for NVIC interrupt table. + */ +void PIOC_Handler(void) +{ + pio_handler_process(PIOC, ID_PIOC); +} +#endif + +#ifdef ID_PIOD +/** + * \brief Parallel IO Controller D interrupt handler. + * Redefined PIOD interrupt handler for NVIC interrupt table. + */ +void PIOD_Handler(void) +{ + pio_handler_process(PIOD, ID_PIOD); +} +#endif + +#ifdef ID_PIOE +/** + * \brief Parallel IO Controller E interrupt handler. + * Redefined PIOE interrupt handler for NVIC interrupt table. + */ +void PIOE_Handler(void) +{ + pio_handler_process(PIOE, ID_PIOE); +} +#endif + +#ifdef ID_PIOF +/** + * \brief Parallel IO Controller F interrupt handler. + * Redefined PIOF interrupt handler for NVIC interrupt table. + */ +void PIOF_Handler(void) +{ + pio_handler_process(PIOF, ID_PIOF); +} +#endif + +/** + * \brief Initialize PIO interrupt management logic. + * + * \param p_pio PIO controller base address. + * \param ul_irqn NVIC line number. + * \param ul_priority PIO controller interrupts priority. + */ +void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority) +{ + uint32_t bitmask = 0; + + bitmask = pio_get_interrupt_mask(p_pio); + pio_disable_interrupt(p_pio, 0xFFFFFFFF); + pio_get_interrupt_status(p_pio); + NVIC_DisableIRQ(ul_irqn); + NVIC_ClearPendingIRQ(ul_irqn); + NVIC_SetPriority(ul_irqn, ul_priority); + NVIC_EnableIRQ(ul_irqn); + pio_enable_interrupt(p_pio, bitmask); +} diff --git a/SAM3S4B/src/ASF/drivers1/pio/pio_handler.h b/SAM3S4B/src/ASF/drivers1/pio/pio_handler.h new file mode 100644 index 0000000..bdf3e0b --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pio/pio_handler.h @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Parallel Input/Output (PIO) interrupt handler for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef PIO_HANDLER_H_INCLUDED +#define PIO_HANDLER_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void pio_handler_process(Pio *p_pio, uint32_t ul_id); +void pio_handler_set_priority(Pio *p_pio, IRQn_Type ul_irqn, uint32_t ul_priority); +uint32_t pio_handler_set(Pio *p_pio, uint32_t ul_id, uint32_t ul_mask, + uint32_t ul_attr, void (*p_handler) (uint32_t, uint32_t)); +uint32_t pio_handler_set_pin(uint32_t ul_pin, uint32_t ul_flag, + void (*p_handler) (uint32_t, uint32_t)); + +#if (SAM3S || SAM4S || SAM4E) +void pio_capture_handler_set(void (*p_handler)(Pio *)); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* PIO_HANDLER_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/pmc/pmc.c b/SAM3S4B/src/ASF/drivers1/pmc/pmc.c new file mode 100644 index 0000000..df2eeb7 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pmc/pmc.c @@ -0,0 +1,1294 @@ +/** + * \file + * + * \brief Power Management Controller (PMC) driver for SAM. + * + * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "pmc.h" + +#if (SAM3N) +# define MAX_PERIPH_ID 31 +#elif (SAM3XA) +# define MAX_PERIPH_ID 44 +#elif (SAM3U) +# define MAX_PERIPH_ID 29 +#elif (SAM3S || SAM4S) +# define MAX_PERIPH_ID 34 +#elif (SAM4E) +# define MAX_PERIPH_ID 47 +#elif (SAM4N) +# define MAX_PERIPH_ID 31 +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_pmc_group Power Management Controller (PMC) + * + * \par Purpose + * + * The Power Management Controller (PMC) optimizes power consumption by + * controlling all system and user peripheral clocks. The PMC enables/disables + * the clock inputs to many of the peripherals and the Cortex-M Processor. + * + * @{ + */ + +/** + * \brief Set the prescaler of the MCK. + * + * \param ul_pres Prescaler value. + */ +void pmc_mck_set_prescaler(uint32_t ul_pres) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} + +/** + * \brief Set the source of the MCK. + * + * \param ul_source Source selection value. + */ +void pmc_mck_set_source(uint32_t ul_source) +{ + PMC->PMC_MCKR = + (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); +} + +/** + * \brief Switch master clock source selection to slow clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_SLOW_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch master clock source selection to main clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_MAIN_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch master clock source selection to PLLA clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLA_CLK; + + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +#if (SAM3S || SAM4S) +/** + * \brief Switch master clock source selection to PLLB clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_PLLB_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +#if (SAM3XA || SAM3U) +/** + * \brief Switch master clock source selection to UPLL clock. + * + * \param ul_pres Processor clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | + PMC_MCKR_CSS_UPLL_CLK; + for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +/** + * \brief Switch slow clock source selection to external 32k (Xtal or Bypass). + * + * \note This function disables the PLLs. + * + * \note Switching SCLK back to 32krc is only possible by shutting down the + * VDDIO power supply. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + */ +void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass) +{ + /* Set Bypass mode if required */ + if (ul_bypass == 1) { + SUPC->SUPC_MR |= SUPC_MR_KEY(SUPC_KEY_VALUE) | + SUPC_MR_OSCBYPASS; + } + + SUPC->SUPC_CR = SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_XTALSEL; +} + +/** + * \brief Check if the external 32k Xtal is ready. + * + * \retval 1 External 32k Xtal is ready. + * \retval 0 External 32k Xtal is not ready. + */ +uint32_t pmc_osc_is_ready_32kxtal(void) +{ + return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) + && (PMC->PMC_SR & PMC_SR_OSCSELS)); +} + +/** + * \brief Switch main clock source selection to internal fast RC. + * + * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz). + * + * \retval 0 Success. + * \retval 1 Timeout error. + * \retval 2 Invalid frequency. + */ +void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf) +{ + uint32_t ul_needXTEN = 0; + + /* Enable Fast RC oscillator but DO NOT switch to RC now */ + if (PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | + PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN | + ul_moscrcf; + } else { + ul_needXTEN = 1; + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | + PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCRCEN | + CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST_Msk | + ul_moscrcf; + } + + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Switch to Fast RC */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | + PMC_CKGR_MOR_KEY_VALUE; + + /* Disable xtal oscillator */ + if (ul_needXTEN) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + PMC_CKGR_MOR_KEY_VALUE; + } +} + +/** + * \brief Enable fast RC oscillator. + * + * \param ul_rc Fast RC oscillator(4/8/12Mhz). + */ +void pmc_osc_enable_fastrc(uint32_t ul_rc) +{ + /* Enable Fast RC oscillator but DO NOT switch to RC now. + * Keep MOSCSEL to 1 */ + PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL | + CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCRCEN | ul_rc; + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); +} + +/** + * \brief Disable the internal fast RC. + */ +void pmc_osc_disable_fastrc(void) +{ + /* Disable Fast RC oscillator */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN & + ~CKGR_MOR_MOSCRCF_Msk) + | PMC_CKGR_MOR_KEY_VALUE; +} + +/** + * \brief Check if the main fastrc is ready. + * + * \retval 0 Xtal is not ready, otherwise ready. + */ +uint32_t pmc_osc_is_ready_fastrc(void) +{ + return (PMC->PMC_SR & PMC_SR_MOSCRCS); +} + +/** + * \brief Enable main XTAL oscillator. + * + * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks. + */ +void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + mor |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN | + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + PMC->CKGR_MOR = mor; + /* Wait the main Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); +} + +/** + * \brief Bypass main XTAL. + */ +void pmc_osc_bypass_main_xtal(void) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + mor |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY; + /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */ + PMC->CKGR_MOR = mor; + /* The MOSCXTS in PMC_SR is automatically set */ +} + +/** + * \brief Disable the main Xtal. + */ +void pmc_osc_disable_main_xtal(void) +{ + uint32_t mor = PMC->CKGR_MOR; + mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN); + PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | mor; +} + +/** + * \brief Check if the main crystal is bypassed. + * + * \retval 0 Xtal is bypassed, otherwise not. + */ +uint32_t pmc_osc_is_bypassed_main_xtal(void) +{ + return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY); +} + +/** + * \brief Check if the main crystal is ready. + * + * \note If main crystal is bypassed, it's always ready. + * + * \retval 0 main crystal is not ready, otherwise ready. + */ +uint32_t pmc_osc_is_ready_main_xtal(void) +{ + return (PMC->PMC_SR & PMC_SR_MOSCXTS); +} + +/** + * \brief Switch main clock source selection to external Xtal/Bypass. + * + * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid + * any system crash. + * + * \note If used in Xtal mode, the Xtal is automatically enabled. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time) +{ + /* Enable Main Xtal oscillator */ + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTBY | + CKGR_MOR_MOSCSEL; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCXTEN | + CKGR_MOR_MOSCXTST(ul_xtal_startup_time); + /* Wait the Xtal to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)); + + PMC->CKGR_MOR |= PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_MOSCSEL; + } +} + +/** + * \brief Disable the external Xtal. + * + * \param ul_bypass 0 for Xtal, 1 for bypass. + */ +void pmc_osc_disable_xtal(uint32_t ul_bypass) +{ + /* Disable xtal oscillator */ + if (ul_bypass) { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) | + PMC_CKGR_MOR_KEY_VALUE; + } else { + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) | + PMC_CKGR_MOR_KEY_VALUE; + } +} + +/** + * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one + * of Xtal, bypass or internal RC. + * + * \retval 1 Xtal is ready. + * \retval 0 Xtal is not ready. + */ +uint32_t pmc_osc_is_ready_mainck(void) +{ + return PMC->PMC_SR & PMC_SR_MOSCSELS; +} + +/** + * \brief Select Main Crystal or internal RC as main clock source. + * + * \note This function will not enable/disable RC or Main Crystal. + * + * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal. + */ +void pmc_mainck_osc_select(uint32_t ul_xtal_rc) +{ + uint32_t mor = PMC->CKGR_MOR; + if (ul_xtal_rc) { + mor |= CKGR_MOR_MOSCSEL; + } else { + mor &= ~CKGR_MOR_MOSCSEL; + } + PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | mor; +} + +/** + * \brief Enable PLLA clock. + * + * \param mula PLLA multiplier. + * \param pllacount PLLA counter. + * \param diva Divider. + */ +void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva) +{ + /* first disable the PLL to unlock the lock */ + pmc_disable_pllack(); + + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) | + CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula); + while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0); +} + +/** + * \brief Disable PLLA clock. + */ +void pmc_disable_pllack(void) +{ + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0); +} + +/** + * \brief Is PLLA locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_pllack(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKA); +} + +#if (SAM3S || SAM4S) +/** + * \brief Enable PLLB clock. + * + * \param mulb PLLB multiplier. + * \param pllbcount PLLB counter. + * \param divb Divider. + */ +void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb) +{ + /* first disable the PLL to unlock the lock */ + pmc_disable_pllbck(); + + PMC->CKGR_PLLBR = + CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount) + | CKGR_PLLBR_MULB(mulb); + while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0); +} + +/** + * \brief Disable PLLB clock. + */ +void pmc_disable_pllbck(void) +{ + PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0); +} + +/** + * \brief Is PLLB locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_pllbck(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKB); +} +#endif + +#if (SAM3XA || SAM3U) +/** + * \brief Enable UPLL clock. + */ +void pmc_enable_upll_clock(void) +{ + PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN; + + /* Wait UTMI PLL Lock Status */ + while (!(PMC->PMC_SR & PMC_SR_LOCKU)); +} + +/** + * \brief Disable UPLL clock. + */ +void pmc_disable_upll_clock(void) +{ + PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN; +} + +/** + * \brief Is UPLL locked? + * + * \retval 0 Not locked. + * \retval 1 Locked. + */ +uint32_t pmc_is_locked_upll(void) +{ + return (PMC->PMC_SR & PMC_SR_LOCKU); +} +#endif + +/** + * \brief Enable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_enable_periph_clk(uint32_t ul_id) +{ + if (ul_id > MAX_PERIPH_ID) { + return 1; + } + + if (ul_id < 32) { + if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) { + PMC->PMC_PCER0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) { + PMC->PMC_PCER1 = 1 << ul_id; + } +#endif + } + + return 0; +} + +/** + * \brief Disable the specified peripheral clock. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Success. + * \retval 1 Invalid parameter. + */ +uint32_t pmc_disable_periph_clk(uint32_t ul_id) +{ + if (ul_id > MAX_PERIPH_ID) { + return 1; + } + + if (ul_id < 32) { + if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) { + PMC->PMC_PCDR0 = 1 << ul_id; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) { + PMC->PMC_PCDR1 = 1 << ul_id; + } +#endif + } + return 0; +} + +/** + * \brief Enable all peripheral clocks. + */ +void pmc_enable_all_periph_clk(void) +{ + PMC->PMC_PCER0 = PMC_MASK_STATUS0; + while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0); + +#if (SAM3S || SAM3XA || SAM4S || SAM4E) + PMC->PMC_PCER1 = PMC_MASK_STATUS1; + while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1); +#endif +} + +/** + * \brief Disable all peripheral clocks. + */ +void pmc_disable_all_periph_clk(void) +{ + PMC->PMC_PCDR0 = PMC_MASK_STATUS0; + while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0); + +#if (SAM3S || SAM3XA || SAM4S || SAM4E) + PMC->PMC_PCDR1 = PMC_MASK_STATUS1; + while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0); +#endif +} + +/** + * \brief Check if the specified peripheral clock is enabled. + * + * \note The ID must NOT be shifted (i.e., 1 << ID_xxx). + * + * \param ul_id Peripheral ID (ID_xxx). + * + * \retval 0 Peripheral clock is disabled or unknown. + * \retval 1 Peripheral clock is enabled. + */ +uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id) +{ + if (ul_id > MAX_PERIPH_ID) { + return 0; + } + +#if (SAM3S || SAM3XA || SAM4S || SAM4E) + if (ul_id < 32) { +#endif + if ((PMC->PMC_PCSR0 & (1u << ul_id))) { + return 1; + } else { + return 0; + } +#if (SAM3S || SAM3XA || SAM4S || SAM4E) + } else { + ul_id -= 32; + if ((PMC->PMC_PCSR1 & (1u << ul_id))) { + return 1; + } else { + return 0; + } + } +#endif +} + +/** + * \brief Set the prescaler for the specified programmable clock. + * + * \param ul_id Peripheral ID. + * \param ul_pres Prescaler value. + */ +void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres) +{ + PMC->PMC_PCK[ul_id] = + (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres; + while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) + && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); +} + +/** + * \brief Set the source oscillator for the specified programmable clock. + * + * \param ul_id Peripheral ID. + * \param ul_source Source selection value. + */ +void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source) +{ + PMC->PMC_PCK[ul_id] = + (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source; + while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id)) + && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id))); +} + +/** + * \brief Switch programmable clock source selection to slow clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch programmable clock source selection to main clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +/** + * \brief Switch programmable clock source selection to PLLA clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} + +#if (SAM3S || SAM4S) +/** + * \brief Switch programmable clock source selection to PLLB clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +#if (SAM3XA || SAM3U) +/** + * \brief Switch programmable clock source selection to UPLL clock. + * + * \param ul_id Id of the programmable clock. + * \param ul_pres Programmable clock prescaler. + * + * \retval 0 Success. + * \retval 1 Timeout error. + */ +uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres) +{ + uint32_t ul_timeout; + + PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres; + for (ul_timeout = PMC_TIMEOUT; + !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); + --ul_timeout) { + if (ul_timeout == 0) { + return 1; + } + } + + return 0; +} +#endif + +/** + * \brief Enable the specified programmable clock. + * + * \param ul_id Id of the programmable clock. + */ +void pmc_enable_pck(uint32_t ul_id) +{ + PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id; +} + +/** + * \brief Disable the specified programmable clock. + * + * \param ul_id Id of the programmable clock. + */ +void pmc_disable_pck(uint32_t ul_id) +{ + PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id; +} + +/** + * \brief Enable all programmable clocks. + */ +void pmc_enable_all_pck(void) +{ + PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2; +} + +/** + * \brief Disable all programmable clocks. + */ +void pmc_disable_all_pck(void) +{ + PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2; +} + +/** + * \brief Check if the specified programmable clock is enabled. + * + * \param ul_id Id of the programmable clock. + * + * \retval 0 Programmable clock is disabled or unknown. + * \retval 1 Programmable clock is enabled. + */ +uint32_t pmc_is_pck_enabled(uint32_t ul_id) +{ + if (ul_id > 2) { + return 0; + } + + return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id)); +} + +#if (SAM3S || SAM3XA || SAM4S || SAM4E) +/** + * \brief Switch UDP (USB) clock source selection to PLLA clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv); +} +#endif + +#if (SAM3S || SAM4S) +/** + * \brief Switch UDP (USB) clock source selection to PLLB clock. + * + * \param ul_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS; +} +#endif + +#if (SAM3XA) +/** + * \brief Switch UDP (USB) clock source selection to UPLL clock. + * + * \param dw_usbdiv Clock divisor. + */ +void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv) +{ + PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv); +} +#endif + +#if (SAM3S || SAM3XA || SAM4S || SAM4E) +/** + * \brief Enable UDP (USB) clock. + */ +void pmc_enable_udpck(void) +{ +# if (SAM3S || SAM4S || SAM4E) + PMC->PMC_SCER = PMC_SCER_UDP; +# else + PMC->PMC_SCER = PMC_SCER_UOTGCLK; +# endif +} + +/** + * \brief Disable UDP (USB) clock. + */ +void pmc_disable_udpck(void) +{ +# if (SAM3S || SAM4S || SAM4E) + PMC->PMC_SCDR = PMC_SCDR_UDP; +# else + PMC->PMC_SCDR = PMC_SCDR_UOTGCLK; +# endif +} +#endif + +/** + * \brief Enable PMC interrupts. + * + * \param ul_sources Interrupt sources bit map. + */ +void pmc_enable_interrupt(uint32_t ul_sources) +{ + PMC->PMC_IER = ul_sources; +} + +/** + * \brief Disable PMC interrupts. + * + * \param ul_sources Interrupt sources bit map. + */ +void pmc_disable_interrupt(uint32_t ul_sources) +{ + PMC->PMC_IDR = ul_sources; +} + +/** + * \brief Get PMC interrupt mask. + * + * \return The interrupt mask value. + */ +uint32_t pmc_get_interrupt_mask(void) +{ + return PMC->PMC_IMR; +} + +/** + * \brief Get current status. + * + * \return The current PMC status. + */ +uint32_t pmc_get_status(void) +{ + return PMC->PMC_SR; +} + +/** + * \brief Set the wake-up inputs for fast startup mode registers + * (event generation). + * + * \param ul_inputs Wake up inputs to enable. + */ +void pmc_set_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_FSMR |= ul_inputs; +} + +/** + * \brief Clear the wake-up inputs for fast startup mode registers + * (remove event generation). + * + * \param ul_inputs Wake up inputs to disable. + */ +void pmc_clr_fast_startup_input(uint32_t ul_inputs) +{ + ul_inputs &= PMC_FAST_STARTUP_Msk; + PMC->PMC_FSMR &= ~ul_inputs; +} + +/** + * \brief Enable Sleep Mode. + * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0) + * + * \param uc_type 0 for wait for interrupt, 1 for wait for event. + * \note For SAM4S and SAM4E series, since only WFI is effective, uc_type = 1 + * will be treated as uc_type = 0. + */ +void pmc_enable_sleepmode(uint8_t uc_type) +{ +#if !defined(SAM4S) || !defined(SAM4E) || !defined(SAM4N) + PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode +#endif + SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep + +#if (SAM4S || SAM4E || SAM4N) + UNUSED(uc_type); + __WFI(); +#else + if (uc_type == 0) { + __WFI(); + } else { + __WFE(); + } +#endif +} + +#if (SAM4S || SAM4E || SAM4N) +static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN; +/** + * \brief Set the embedded flash state in wait mode + * + * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode, + * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode. + */ +void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state) +{ + ul_flash_in_wait_mode = ul_flash_state; +} + +/** + * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + + * (SLEEPDEEP bit = 0) + FLPM + */ +void pmc_enable_waitmode(void) +{ + uint32_t i; + + /* Flash in Deep Power Down mode */ + i = PMC->PMC_FSMR; + i &= ~PMC_FSMR_FLPM_Msk; + i |= ul_flash_in_wait_mode; + PMC->PMC_FSMR = i; + + /* Clear SLEEPDEEP bit */ + SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; + + /* Backup FWS setting and set Flash Wait State at 0 */ +#if defined(ID_EFC) + uint32_t fmr_backup; + fmr_backup = EFC->EEFC_FMR; + EFC->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk; +#endif +#if defined(ID_EFC0) + uint32_t fmr0_backup; + fmr0_backup = EFC0->EEFC_FMR; + EFC0->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk; +#endif +#if defined(ID_EFC1) + uint32_t fmr1_backup; + fmr1_backup = EFC1->EEFC_FMR; + EFC1->EEFC_FMR &= (uint32_t) ~ EEFC_FMR_FWS_Msk; +#endif + + /* Set the WAITMODE bit = 1 */ + PMC->CKGR_MOR |= CKGR_MOR_KEY(0x37u) | CKGR_MOR_WAITMODE; + + /* Waiting for Master Clock Ready MCKRDY = 1 */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + + /* Waiting for MOSCRCEN bit cleared is strongly recommended + * to ensure that the core will not execute undesired instructions + */ + for (i = 0; i < 500; i++) { + __NOP(); + } + while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); + + /* Restore EFC FMR setting */ +#if defined(ID_EFC) + EFC->EEFC_FMR = fmr_backup; +#endif +#if defined(ID_EFC0) + EFC0->EEFC_FMR = fmr0_backup; +#endif +#if defined(ID_EFC1) + EFC1->EEFC_FMR = fmr1_backup; +#endif +} +#else +/** + * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) + + * (LPM bit = 1) + */ +void pmc_enable_waitmode(void) +{ + uint32_t i; + + PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */ + SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */ + __WFE(); + + /* Waiting for MOSCRCEN bit cleared is strongly recommended + * to ensure that the core will not execute undesired instructions + */ + for (i = 0; i < 500; i++) { + __NOP(); + } + while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN)); +} +#endif + +/** + * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) + + * (SLEEPDEEP bit = 1) + */ +void pmc_enable_backupmode(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +#if (SAM4S || SAM4E || SAM4N) + SUPC->SUPC_CR = SUPC_CR_KEY(SUPC_KEY_VALUE) | SUPC_CR_VROFF_STOP_VREG; +#else + __WFE(); +#endif +} + +/** + * \brief Enable Clock Failure Detector. + */ +void pmc_enable_clock_failure_detector(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR; + + PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_CFDEN | ul_reg; +} + +/** + * \brief Disable Clock Failure Detector. + */ +void pmc_disable_clock_failure_detector(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN); + + PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | ul_reg; +} + +#if SAM4N +/** + * \brief Enable Slow Crystal Oscillator Frequency Monitoring. + */ +void pmc_enable_sclk_osc_freq_monitor(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR; + + PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | CKGR_MOR_XT32KFME | ul_reg; +} + +/** + * \brief Disable Slow Crystal Oscillator Frequency Monitoring. + */ +void pmc_disable_sclk_osc_freq_monitor(void) +{ + uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME); + + PMC->CKGR_MOR = PMC_CKGR_MOR_KEY_VALUE | ul_reg; +} +#endif + +/** + * \brief Enable or disable write protect of PMC registers. + * + * \param ul_enable 1 to enable, 0 to disable. + */ +void pmc_set_writeprotect(uint32_t ul_enable) +{ + if (ul_enable) { + PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE | PMC_WPMR_WPEN; + } else { + PMC->PMC_WPMR = PMC_WPMR_WPKEY_VALUE; + } +} + +/** + * \brief Return write protect status. + * + * \retval 0 Protection disabled. + * \retval 1 Protection enabled. + */ +uint32_t pmc_get_writeprotect_status(void) +{ + return PMC->PMC_WPMR & PMC_WPMR_WPEN; +} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/SAM3S4B/src/ASF/drivers1/pmc/pmc.h b/SAM3S4B/src/ASF/drivers1/pmc/pmc.h new file mode 100644 index 0000000..49857dd --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pmc/pmc.h @@ -0,0 +1,484 @@ +/** + * \file + * + * \brief Power Management Controller (PMC) driver for SAM. + * + * Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef PMC_H_INCLUDED +#define PMC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Bit mask for peripheral clocks (PCER0) */ +#define PMC_MASK_STATUS0 (0xFFFFFFFC) + +/** Bit mask for peripheral clocks (PCER1) */ +#define PMC_MASK_STATUS1 (0xFFFFFFFF) + +/** Loop counter timeout value */ +#define PMC_TIMEOUT (2048) + +/** Key to unlock CKGR_MOR register */ +#define PMC_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) + +/** Key used to write SUPC registers */ +#define SUPC_KEY_VALUE ((uint32_t) 0xA5) + +/** Mask to access fast startup input */ +#define PMC_FAST_STARTUP_Msk (0x7FFFFu) + +/** PMC_WPMR Write Protect KEY, unlock it */ +#define PMC_WPMR_WPKEY_VALUE PMC_WPMR_WPKEY((uint32_t) 0x504D43) + +/** Using external oscillator */ +#define PMC_OSC_XTAL 0 + +/** Oscillator in bypass mode */ +#define PMC_OSC_BYPASS 1 + +#define PMC_PCK_0 0 /* PCK0 ID */ +#define PMC_PCK_1 1 /* PCK1 ID */ +#define PMC_PCK_2 2 /* PCK2 ID */ + +#if SAM4S || SAM4E || SAM4N +/** Flash state in Wait Mode */ +#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY +#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN +#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE +#endif + +/** Convert startup time from us to MOSCXTST */ +#define pmc_us_to_moscxtst(startup_us, slowck_freq) \ + ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \ + (startup_us * slowck_freq / 8 / 1000000) : 0xFF) + +/** + * \name Master clock (MCK) Source and Prescaler configuration + * + * \note The following functions may be used to select the clock source and + * prescaler for the master clock. + */ +//@{ + +void pmc_mck_set_prescaler(uint32_t ul_pres); +void pmc_mck_set_source(uint32_t ul_source); +uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres); +uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres); +uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres); +#if (SAM3S || SAM4S) +uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres); +#endif +#if (SAM3XA || SAM3U) +uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres); +#endif +#if (SAM4S || SAM4E || SAM4N) +void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state); +#endif + + +//@} + +/** + * \name Slow clock (SLCK) oscillator and configuration + * + */ +//@{ + +void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass); +uint32_t pmc_osc_is_ready_32kxtal(void); + +//@} + +/** + * \name Main Clock (MAINCK) oscillator and configuration + * + */ +//@{ + +void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf); +void pmc_osc_enable_fastrc(uint32_t ul_rc); +void pmc_osc_disable_fastrc(void); +uint32_t pmc_osc_is_ready_fastrc(void); +void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time); +void pmc_osc_bypass_main_xtal(void); +void pmc_osc_disable_main_xtal(void); +uint32_t pmc_osc_is_bypassed_main_xtal(void); +uint32_t pmc_osc_is_ready_main_xtal(void); +void pmc_switch_mainck_to_xtal(uint32_t ul_bypass, + uint32_t ul_xtal_startup_time); +void pmc_osc_disable_xtal(uint32_t ul_bypass); +uint32_t pmc_osc_is_ready_mainck(void); +void pmc_mainck_osc_select(uint32_t ul_xtal_rc); + +//@} + +/** + * \name PLL oscillator and configuration + * + */ +//@{ + +void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva); +void pmc_disable_pllack(void); +uint32_t pmc_is_locked_pllack(void); + +#if (SAM3S || SAM4S) +void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb); +void pmc_disable_pllbck(void); +uint32_t pmc_is_locked_pllbck(void); +#endif + +#if (SAM3XA || SAM3U) +void pmc_enable_upll_clock(void); +void pmc_disable_upll_clock(void); +uint32_t pmc_is_locked_upll(void); +#endif + +//@} + +/** + * \name Peripherals clock configuration + * + */ +//@{ + +uint32_t pmc_enable_periph_clk(uint32_t ul_id); +uint32_t pmc_disable_periph_clk(uint32_t ul_id); +void pmc_enable_all_periph_clk(void); +void pmc_disable_all_periph_clk(void); +uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id); + +//@} + +/** + * \name Programmable clock Source and Prescaler configuration + * + * The following functions may be used to select the clock source and + * prescaler for the specified programmable clock. + */ +//@{ + +void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres); +void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source); +uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres); +uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres); +uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres); +#if (SAM3S || SAM4S) +uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres); +#endif +#if (SAM3XA || SAM3U) +uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres); +#endif +void pmc_enable_pck(uint32_t ul_id); +void pmc_disable_pck(uint32_t ul_id); +void pmc_enable_all_pck(void); +void pmc_disable_all_pck(void); +uint32_t pmc_is_pck_enabled(uint32_t ul_id); + +//@} + +/** + * \name USB clock configuration + * + */ +//@{ + +#if (SAM3S || SAM3XA || SAM4S || SAM4E) +void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv); +#endif +#if (SAM3S || SAM4S) +void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv); +#endif +#if (SAM3XA) +void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv); +#endif +#if (SAM3S || SAM3XA || SAM4S || SAM4E) +void pmc_enable_udpck(void); +void pmc_disable_udpck(void); +#endif + +//@} + +/** + * \name Interrupt and status management + * + */ +//@{ + +void pmc_enable_interrupt(uint32_t ul_sources); +void pmc_disable_interrupt(uint32_t ul_sources); +uint32_t pmc_get_interrupt_mask(void); +uint32_t pmc_get_status(void); + +//@} + +/** + * \name Power management + * + * The following functions are used to configure sleep mode and additional + * wake up inputs. + */ +//@{ + +void pmc_set_fast_startup_input(uint32_t ul_inputs); +void pmc_clr_fast_startup_input(uint32_t ul_inputs); +void pmc_enable_sleepmode(uint8_t uc_type); +void pmc_enable_waitmode(void); +void pmc_enable_backupmode(void); + +//@} + +/** + * \name Failure detector + * + */ +//@{ + +void pmc_enable_clock_failure_detector(void); +void pmc_disable_clock_failure_detector(void); + +//@} + +#if SAM4N +/** + * \name Slow Crystal Oscillator Frequency Monitoring + * + */ +//@{ + +void pmc_enable_sclk_osc_freq_monitor(void); +void pmc_disable_sclk_osc_freq_monitor(void); + +//@} +#endif + +/** + * \name Write protection + * + */ +//@{ + +void pmc_set_writeprotect(uint32_t ul_enable); +uint32_t pmc_get_writeprotect_status(void); + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +//! @} + +/** + * \page sam_pmc_quickstart Quick start guide for the SAM PMC module + * + * This is the quick start guide for the \ref pmc_group "PMC module", with + * step-by-step instructions on how to configure and use the driver in a + * selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \section pmc_use_cases PMC use cases + * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources + * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks + * + * \section pmc_basic_use_case Basic use case - Switch Main Clock sources + * In this use case, the PMC module is configured for a variety of system clock + * sources and speeds. A LED is used to visually indicate the current clock + * speed as the source is switched. + * + * \section pmc_basic_use_case_setup Setup + * + * \subsection pmc_basic_use_case_setup_prereq Prerequisites + * -# \ref gpio_group "General Purpose I/O Management (gpio)" + * + * \subsection pmc_basic_use_case_setup_code Code + * The following function needs to be added to the user application, to flash a + * board LED a variable number of times at a rate given in CPU ticks. + * + * \code + * #define FLASH_TICK_COUNT 0x00012345 + * + * void flash_led(uint32_t tick_count, uint8_t flash_count) + * { + * SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; + * SysTick->LOAD = tick_count; + * + * while (flash_count--) + * { + * gpio_toggle_pin(LED0_GPIO); + * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); + * gpio_toggle_pin(LED0_GPIO); + * while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)); + * } + * } + * \endcode + * + * \section pmc_basic_use_case_usage Use case + * + * \subsection pmc_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + * for (;;) + * { + * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + * flash_led(FLASH_TICK_COUNT, 5); + * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + * flash_led(FLASH_TICK_COUNT, 5); + * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + * flash_led(FLASH_TICK_COUNT, 5); + * pmc_switch_mainck_to_xtal(0); + * flash_led(FLASH_TICK_COUNT, 5); + * } + * \endcode + * + * \subsection pmc_basic_use_case_usage_flow Workflow + * -# Wrap the code in an infinite loop: + * \code + * for (;;) + * \endcode + * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash + * a LED on the board several times: + * \code + * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz); + * flash_led(FLASH_TICK_COUNT, 5); + * \endcode + * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash + * a LED on the board several times: + * \code + * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz); + * flash_led(FLASH_TICK_COUNT, 5); + * \endcode + * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash + * a LED on the board several times: + * \code + * pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + * flash_led(FLASH_TICK_COUNT, 5); + * \endcode + * -# Switch the Master CPU frequency to the external crystal oscillator, flash + * a LED on the board several times: + * \code + * pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US); + * flash_led(FLASH_TICK_COUNT, 5); + * \endcode + */ + +/** + * \page pmc_use_case_2 Use case #2 - Configure Programmable Clocks + * In this use case, the PMC module is configured to start the Slow Clock from + * an attached 32KHz crystal, and start one of the Programmable Clock modules + * sourced from the Slow Clock divided down with a prescale factor of 64. + * + * \section pmc_use_case_2_setup Setup + * + * \subsection pmc_use_case_2_setup_prereq Prerequisites + * -# \ref pio_group "Parallel Input/Output Controller (pio)" + * + * \subsection pmc_use_case_2_setup_code Code + * The following code must be added to the user application: + * \code + * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); + * \endcode + * + * \subsection pmc_use_case_2_setup_code_workflow Workflow + * -# Configure the PCK1 pin to output on a specific port pin (in this case, + * PIOA pin 17) of the microcontroller. + * \code + * pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17); + * \endcode + * \note The peripheral selection and pin will vary according to your selected + * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O + * Lines" of your device's datasheet. + * + * \section pmc_use_case_2_usage Use case + * The generated PCK1 clock output can be viewed on an oscilloscope attached to + * the correct pin of the microcontroller. + * + * \subsection pmc_use_case_2_usage_code Example code + * Add to application C-file: + * \code + * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); + * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); + * pmc_enable_pck(PMC_PCK_1); + * + * for (;;) + * { + * // Do Nothing + * } + * \endcode + * + * \subsection pmc_use_case_2_usage_flow Workflow + * -# Switch the Slow Clock source input to an external 32KHz crystal: + * \code + * pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL); + * \endcode + * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock, + * with a prescaler of 64: + * \code + * pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64); + * \endcode + * -# Enable Programmable Clock module PCK1: + * \code + * pmc_enable_pck(PMC_PCK_1); + * \endcode + * -# Enter an infinite loop: + * \code + * for (;;) + * { + * // Do Nothing + * } + * \endcode + */ + +#endif /* PMC_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/pmc/sleep.c b/SAM3S4B/src/ASF/drivers1/pmc/sleep.c new file mode 100644 index 0000000..eee251f --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pmc/sleep.c @@ -0,0 +1,251 @@ +/** + * \file + * + * \brief Sleep mode access + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include "sleep.h" + +/* SAM3 and SAM4 series */ +#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N) +# include "pmc.h" +# include "board.h" + +/* Checking board configuration of main clock xtal statup time */ +#if !defined(BOARD_OSC_STARTUP_US) +# warning The board main clock xtal statup time has not been defined. Using default settings. +# define BOARD_OSC_STARTUP_US (15625UL) +#endif + +/** + * Save clock settings and shutdown PLLs + */ +__always_inline static void pmc_save_clock_settings( + uint32_t *p_osc_setting, + uint32_t *p_pll0_setting, + uint32_t *p_pll1_setting, + uint32_t *p_mck_setting) +{ + if (p_osc_setting) { + *p_osc_setting = PMC->CKGR_MOR; + } + if (p_pll0_setting) { + *p_pll0_setting = PMC->CKGR_PLLAR; + } + if (p_pll1_setting) { +#if (SAM3S || SAM4S) + *p_pll1_setting = PMC->CKGR_PLLBR; +#elif (SAM3U || SAM3XA) + *p_pll1_setting = PMC->CKGR_UCKR; +#else + *p_pll1_setting = 0; +#endif + } + if (p_mck_setting) { + *p_mck_setting = PMC->PMC_MCKR; + } + + /* Switch MCK to internal 4/8/12M RC for fast wakeup + and disable unused clock for power saving. */ + pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1); + pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz); + pmc_osc_disable_xtal(0); + pmc_disable_pllack(); +#if (SAM3S || SAM4S) + pmc_disable_pllbck(); +#elif (SAM3U || SAM3XA) + pmc_disable_upll_clock(); +#endif + pmc_switch_mck_to_mainck(PMC_MCKR_PRES_CLK_1); +} + +/** + * Restore clock settings + */ +__always_inline static void pmc_restore_clock_setting( + uint32_t osc_setting, + uint32_t pll0_setting, + uint32_t pll1_setting, + uint32_t mck_setting) +{ + uint32_t mckr; + uint32_t pll_sr = 0; + + /* Switch MCK to slow clock */ + pmc_switch_mck_to_sclk(PMC_MCKR_PRES_CLK_1); + /* Switch mainck to external xtal */ + if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) { + /* Bypass mode */ + pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS, + pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, + CHIP_FREQ_SLCK_RC)); + pmc_osc_disable_fastrc(); + } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) { + /* External XTAL */ + pmc_switch_mainck_to_xtal(PMC_OSC_XTAL, + pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US, + CHIP_FREQ_SLCK_RC)); + pmc_osc_disable_fastrc(); + } + + if (pll0_setting & CKGR_PLLAR_MULA_Msk) { + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting; + pll_sr |= PMC_SR_LOCKA; + } +#if (SAM3S || SAM4S) + if (pll1_setting & CKGR_PLLBR_MULB_Msk) { + PMC->CKGR_PLLBR = pll1_setting; + pll_sr |= PMC_SR_LOCKB; + } +#elif (SAM3U || SAM3XA) + if (pll1_setting & CKGR_UCKR_UPLLEN) { + PMC->CKGR_UCKR = pll1_setting; + pll_sr |= PMC_SR_LOCKU; + } +#else + UNUSED(pll1_setting); +#endif + /* Wait MCK source ready */ + switch(mck_setting & PMC_MCKR_CSS_Msk) { + case PMC_MCKR_CSS_PLLA_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKA)); + break; +#if (SAM3S || SAM4S) + case PMC_MCKR_CSS_PLLB_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKB)); + break; +#elif (SAM3U || SAM3XA) + case PMC_MCKR_CSS_UPLL_CLK: + while (!(PMC->PMC_SR & PMC_SR_LOCKU)); + break; +#endif + } + + /* Switch to faster clock */ + mckr = PMC->PMC_MCKR; + /* Set PRES */ + PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk) + | (mck_setting & PMC_MCKR_PRES_Msk); + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + /* Set CSS and others */ + PMC->PMC_MCKR = mck_setting; + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)); + /* Waiting all restored PLLs ready */ + while (!(PMC->PMC_SR & pll_sr)); +} + +/** If clocks are switched to FASTRC for WAIT mode */ +static volatile bool b_is_fastrc_used = false; +/** Callback invoked once when clocks are restored */ +static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL; + +void pmc_sleep(int sleep_mode) +{ + switch (sleep_mode) { + case SAM_PM_SMODE_SLEEP_WFI: + case SAM_PM_SMODE_SLEEP_WFE: +#if (SAM4S || SAM4E || SAM4N) + SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; + cpu_irq_enable(); + __WFI(); + break; +#else + PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM; + SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP; + cpu_irq_enable(); + if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI) + __WFI(); + else + __WFE(); + break; +#endif + case SAM_PM_SMODE_WAIT: { + uint32_t mor, pllr0, pllr1, mckr; + cpu_irq_disable(); + b_is_fastrc_used = true; + pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr); + + /* Enter wait mode */ + cpu_irq_enable(); + pmc_enable_waitmode(); + + cpu_irq_disable(); + pmc_restore_clock_setting(mor, pllr0, pllr1, mckr); + b_is_fastrc_used = false; + if (callback_clocks_restored) { + callback_clocks_restored(); + callback_clocks_restored = NULL; + } + cpu_irq_enable(); + break; + } + + case SAM_PM_SMODE_BACKUP: + SCB->SCR |= SCR_SLEEPDEEP; +#if (SAM4S || SAM4E || SAM4N) + SUPC->SUPC_CR = SUPC_CR_KEY(0xA5u) | SUPC_CR_VROFF_STOP_VREG; + cpu_irq_enable(); + __WFI() ; +#else + cpu_irq_enable(); + __WFE() ; +#endif + break; + } +} + +bool pmc_is_wakeup_clocks_restored(void) +{ + return !b_is_fastrc_used; +} + +void pmc_wait_wakeup_clocks_restore( + pmc_callback_wakeup_clocks_restored_t callback) +{ + if (b_is_fastrc_used) { + cpu_irq_disable(); + callback_clocks_restored = callback; + } else if (callback) { + callback(); + } +} + +#endif /* #if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N) */ diff --git a/SAM3S4B/src/ASF/drivers1/pmc/sleep.h b/SAM3S4B/src/ASF/drivers1/pmc/sleep.h new file mode 100644 index 0000000..e95ac12 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/pmc/sleep.h @@ -0,0 +1,122 @@ +/** + * \file + * + * \brief Sleep mode access + * + * Copyright (c) 2012 - 2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef SLEEP_H +#define SLEEP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \defgroup sleep_group Power Manager (PM) + * + * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr + * service. + * + * \note To minimize the code overhead, these functions do not feature + * interrupt-protected access since they are likely to be called inside + * interrupt handlers or in applications where such protection is not + * necessary. If such protection is needed, it must be ensured by the calling + * code. + * + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * \brief Sets the MCU in the specified sleep mode + * \param sleep_mode Sleep mode to set. + */ +#endif +/* SAM3 and SAM4 series */ +#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N) + +# define SAM_PM_SMODE_ACTIVE 0 /**< Active */ +# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */ +# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */ +# define SAM_PM_SMODE_WAIT 3 /**< Wait Mode */ +# define SAM_PM_SMODE_BACKUP 4 /**< Backup Mode */ + +/** (SCR) Sleep deep bit */ +#define SCR_SLEEPDEEP (0x1 << 2) + +/** + * Clocks restored callback function type. + * Registered by routine pmc_wait_wakeup_clocks_restore() + * Callback called when all clocks are restored. + */ +typedef void (*pmc_callback_wakeup_clocks_restored_t) (void); + +/** + * Enter sleep mode + * \param sleep_mode Sleep mode to enter + */ +void pmc_sleep(int sleep_mode); + +/** + * Check if clocks are restored after wakeup + * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC. + * After wakeup clocks should be restored, before that some of the + * ISR should not be served, otherwise there may be timing or clock issue.) + */ +bool pmc_is_wakeup_clocks_restored(void); + +/** + * + * \return true if start waiting + */ +void pmc_wait_wakeup_clocks_restore( + pmc_callback_wakeup_clocks_restored_t callback); + +#endif + +//! @} + +#ifdef __cplusplus +} +#endif + +#endif /* SLEEP_H */ diff --git a/SAM3S4B/src/ASF/drivers1/ssc/ssc.c b/SAM3S4B/src/ASF/drivers1/ssc/ssc.c new file mode 100644 index 0000000..898924b --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/ssc/ssc.c @@ -0,0 +1,922 @@ +/** + * \file + * + * \brief Synchronous Serial Controller (SSC) driver for SAM. + * + * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include "ssc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_ssc_group Synchronous Serial Controller (SSC) + * + * The Synchronous Serial Controller (SSC) provides a synchronous communication + * link with external devices. It supports many serial synchronous communication + * protocols generally used in audio and telecom applications such as I2S, + * Short Frame Sync, Long Frame Sync, etc. + * This is a driver for configuration and use of the SSC peripheral. + * + * @{ + */ + +#define SSC_WPKEY SSC_WPMR_WPKEY(0x535343) + +/** + * \brief Set up clock. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_bitrate Desired bit clock. + * \param ul_mck MCK clock. + * + * \retval SSC_RC_YES Success. + * \retval SSC_RC_NO Invalid input value. + */ +uint32_t ssc_set_clock_divider(Ssc *p_ssc, uint32_t ul_bitrate, + uint32_t ul_mck) +{ + if (ul_mck && ul_bitrate) { + p_ssc->SSC_CMR = SSC_CMR_DIV(((ul_mck + ul_bitrate) / ul_bitrate) >> 1); + return SSC_RC_YES; + } else { + return SSC_RC_NO; + } +} + +/** + * \brief Setup for I2S transmitter. + * + * \note If working in master mode, the divided clock needs to be configured before + * calling this function according to the sample rate and ul_datlen field. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_mode Working mode, SSC_I2S_MASTER_OUT or SSC_I2S_SLAVE_OUT. + * \param ul_cks Source clock selection while working in SSC_I2S_SLAVE_OUT mode. + * \param ul_ch_mode Channel mode, stereo or mono. + * \param ul_datlen Data length for one channel. + */ +//void ssc_i2s_set_transmitter(Ssc *p_ssc, uint32_t ul_mode, +// uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen) +//{ +// clock_opt_t tx_clk_option; +// data_frame_opt_t tx_data_frame_option; + + /* Initialize the local variable. */ +// memset((uint8_t *)&tx_clk_option, 0, sizeof(clock_opt_t)); +// memset((uint8_t *)&tx_data_frame_option, 0, sizeof(data_frame_opt_t)); + + /* Data start: MonoLeft-Falling, MonoRight-Rising, Stero-Edge. */ +// switch (ul_ch_mode) { +// case SSC_AUDIO_MONO_RIGHT: +// tx_clk_option.ul_start_sel = SSC_TCMR_START_RF_RISING; +// break; +// case SSC_AUDIO_MONO_LEFT: +//// tx_clk_option.ul_start_sel = SSC_TCMR_START_RF_FALLING; +// break; +// case SSC_AUDIO_STERO: +// tx_clk_option.ul_start_sel = SSC_TCMR_START_RF_EDGE; +// break; +// } +// if (ul_mode & SSC_I2S_MASTER_OUT) { +// /* Stereo has 2 data words, and mono has only one data word. */ +// if (SSC_AUDIO_STERO == ul_ch_mode) { +// tx_data_frame_option.ul_datnb = 1; +// } else { +// tx_data_frame_option.ul_datnb = 0; +// } + + /* Configure TCMR Settings. */ +// tx_clk_option.ul_cks = SSC_TCMR_CKS_MCK; +// tx_clk_option.ul_cko = SSC_TCMR_CKO_CONTINUOUS; +// tx_clk_option.ul_cki = 0; +// tx_clk_option.ul_ckg = SSC_RCMR_CKG_NONE; +// /* The delay is defined by I2S protocol. */ +// tx_clk_option.ul_sttdly = 1; +// tx_clk_option.ul_period = ul_datlen - 1; + +// /* Configure TFMR Settings. */ +// tx_data_frame_option.ul_datlen = ul_datlen - 1; +// tx_data_frame_option.ul_msbf = SSC_TFMR_MSBF; +// tx_data_frame_option.ul_fslen = ul_datlen - 1; +// tx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NEGATIVE; +// tx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE; +// } else if (ul_mode & SSC_I2S_SLAVE_OUT) { + /* Configure TCMR Settings. */ +// tx_clk_option.ul_cks = ul_cks; +// tx_clk_option.ul_cko = SSC_TCMR_CKO_NONE; +// tx_clk_option.ul_cki = 0; +// tx_clk_option.ul_ckg = SSC_RCMR_CKG_NONE; +// tx_clk_option.ul_sttdly = 1; +// tx_clk_option.ul_period = 0; + + /* Configure TFMR Settings. */ +// tx_data_frame_option.ul_datlen = ul_datlen - 1; +// tx_data_frame_option.ul_msbf = SSC_TFMR_MSBF; +// tx_data_frame_option.ul_fslen = 0; +// tx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NONE; +// tx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE; +// } + /* Configure the default level on TD pin. */ +// ssc_set_td_default_level(p_ssc, 0); + + /* Configure the SSC transmitter. */ +// ssc_set_transmitter(p_ssc, &tx_clk_option, &tx_data_frame_option); +//} + +/** + * \brief Setup for I2S receiver. + * + * \note If working in master mode, the divided clock needs to be configured before + * calling this function according to the sample rate and ul_datlen field. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_mode Working mode, SSC_I2S_MASTER_IN or SSC_I2S_SLAVE_IN. + * \param ul_cks Source clock selection while working in SSC_I2S_SLAVE_IN mode. + * \param ul_ch_mode Channel mode, stereo or mono. + * \param ul_datlen Data length for one channel. + */ +//void ssc_i2s_set_receiver(Ssc *p_ssc, uint32_t ul_mode, +// uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen) +//{ +// clock_opt_t rx_clk_option; +// data_frame_opt_t rx_data_frame_option; + + /* Initialize the local variable. */ +// memset((uint8_t *)&rx_clk_option, 0, sizeof(clock_opt_t)); +// memset((uint8_t *)&rx_data_frame_option, 0, sizeof(data_frame_opt_t)); + + /* Data start: MonoLeft-Falling, MonoRight-Rising, Stero-Edge. */ +// switch (ul_ch_mode) { +// case SSC_AUDIO_MONO_RIGHT: +// rx_clk_option.ul_start_sel = SSC_RCMR_START_RF_RISING; +// break; +// case SSC_AUDIO_MONO_LEFT: +// rx_clk_option.ul_start_sel = SSC_RCMR_START_RF_FALLING; +// break; +// case SSC_AUDIO_STERO: +// rx_clk_option.ul_start_sel = SSC_RCMR_START_RF_EDGE; +// break; +// } +// if (ul_mode & SSC_I2S_MASTER_IN) { +// /* Stereo has 2 data words, and mono has only one data word. */ +// if (SSC_AUDIO_STERO == ul_ch_mode) { +// rx_data_frame_option.ul_datnb = 1; +// } else { +// rx_data_frame_option.ul_datnb = 0; +// } + + /* Configure RCMR Settings. */ +// rx_clk_option.ul_cks = SSC_TCMR_CKS_MCK; +// rx_clk_option.ul_cko = SSC_TCMR_CKO_CONTINUOUS; +// rx_clk_option.ul_cki = 0; +// rx_clk_option.ul_ckg = SSC_RCMR_CKG_NONE; +// rx_clk_option.ul_sttdly = 1; +// rx_clk_option.ul_period = ul_datlen - 1; + + /* Configure RFMR Settings. */ +// rx_data_frame_option.ul_datlen = ul_datlen - 1; +// rx_data_frame_option.ul_msbf = SSC_TFMR_MSBF; +// rx_data_frame_option.ul_fslen = ul_datlen - 1; +// rx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NEGATIVE; +// rx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE; +// } else if (ul_mode & SSC_I2S_SLAVE_IN) { + /* Configure TCMR Settings. */ +// rx_clk_option.ul_cks = ul_cks; +// rx_clk_option.ul_cko = SSC_TCMR_CKO_NONE; +// rx_clk_option.ul_cki = 0; +// rx_clk_option.ul_ckg = SSC_RCMR_CKG_NONE; +// rx_clk_option.ul_sttdly = 1; +// rx_clk_option.ul_period = 0; + + /* Configure TFMR Settings. */ +// rx_data_frame_option.ul_datlen = ul_datlen - 1; +// rx_data_frame_option.ul_msbf = SSC_TFMR_MSBF; +// rx_data_frame_option.ul_fslen = 0; +// rx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NONE; +// rx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE; +// } +// +// /* Configure the SSC receiver. */ +// ssc_set_receiver(p_ssc, &rx_clk_option, &rx_data_frame_option); +//} + +/** + * \brief Reset SSC module. + * + * \param p_ssc Pointer to an SSC instance. + */ +void ssc_reset(Ssc *p_ssc) +{ + p_ssc->SSC_CR = SSC_CR_SWRST; + p_ssc->SSC_CMR = 0; + p_ssc->SSC_RCMR = 0; + p_ssc->SSC_RFMR = 0; + p_ssc->SSC_TCMR = 0; + p_ssc->SSC_TFMR = 0; +} + +/** + * \brief Enable SSC receiver. + * + * \param p_ssc Pointer to an SSC instance. + */ +void ssc_enable_rx(Ssc *p_ssc) +{ + p_ssc->SSC_CR = SSC_CR_RXEN; +} + +/** + * \brief Disable SSC receiver. + * + * \param p_ssc Pointer to an SSC instance. + */ +void ssc_disable_rx(Ssc *p_ssc) +{ + p_ssc->SSC_CR = SSC_CR_RXDIS; +} + +/** + * \brief Enable SSC Transmitter. + * + * \param p_ssc Pointer to an SSC instance. + */ +void ssc_enable_tx(Ssc *p_ssc) +{ + p_ssc->SSC_CR = SSC_CR_TXEN; +} + +/** + * \brief Disable SSC Transmitter. + * + * \param p_ssc Pointer to an SSC instance. + */ +void ssc_disable_tx(Ssc *p_ssc) +{ + p_ssc->SSC_CR = SSC_CR_TXDIS; +} + +/** + * \brief Configure SSC to work in normal mode. + * + * \param p_ssc Pointer to an SSC instance. + */ +//void ssc_set_normal_mode(Ssc *p_ssc) +//{ +// p_ssc->SSC_RFMR &= ~SSC_RFMR_LOOP; +///} + +/** + * \brief Configure SSC to work in loop mode. + * + * \param p_ssc Pointer to an SSC instance. + */ +//void ssc_set_loop_mode(Ssc *p_ssc) +//{ +// p_ssc->SSC_RFMR |= SSC_RFMR_LOOP; +//} + +/** + * \brief Configure SSC receive stop selection. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_sel Compare 0 used or Compare both 0 & 1 used. + */ +//void ssc_set_rx_stop_selection(Ssc *p_ssc, uint32_t ul_sel) +//{ +// if (SSC_RX_STOP_COMPARE_0_1 == ul_sel) { +// p_ssc->SSC_RCMR |= SSC_RCMR_STOP; +// } else if (SSC_RX_STOP_COMPARE_0 == ul_sel) { +// p_ssc->SSC_RCMR &= ~SSC_RCMR_STOP; +// } +//} + +/** + * \brief Configure SSC default level driven on the TD pin while + * out of transmission. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_level The default driven level of TD pin. + */ +//void ssc_set_td_default_level(Ssc *p_ssc, uint32_t ul_level) +//{ +// if (ul_level) { +// p_ssc->SSC_TFMR |= SSC_TFMR_DATDEF; +// } else { +// p_ssc->SSC_TFMR &= ~SSC_TFMR_DATDEF; +// } +//} + +/** + * \brief The TD line is driven with the SSC_TSHR register value + * during the transmission of the Transmit Frame Sync Signal. + * + * \param p_ssc Pointer to an SSC instance. + */ +void ssc_enable_tx_frame_sync_data(Ssc *p_ssc) +{ + p_ssc->SSC_TFMR |= SSC_TFMR_FSDEN; +} + +/** + * \brief The TD line is driven with the default value during the Transmit + * Frame Sync signal. + * + * \param p_ssc Pointer to an SSC instance. + */ +void ssc_disable_tx_frame_sync_data(Ssc *p_ssc) +{ + p_ssc->SSC_TFMR &= ~SSC_TFMR_FSDEN; +} + +/** + * \brief Configure SSC receiver clock mode and date frame configuration. + * + * \param p_ssc Pointer to an SSC instance. + * \param p_rx_clk_opt Pointer to the receiver clock configuration structure. + * \param p_rx_data_frame Pointer to the receiver data frame configuration structure. + */ +//void ssc_set_receiver(Ssc *p_ssc, clock_opt_t *p_rx_clk_opt, +// data_frame_opt_t *p_rx_data_frame) +//{ +// if (p_rx_clk_opt == NULL) { +// p_ssc->SSC_RCMR = 0; +// } else { +// p_ssc->SSC_RCMR |= p_rx_clk_opt->ul_cks | +// p_rx_clk_opt->ul_cko | p_rx_clk_opt->ul_cki | +// p_rx_clk_opt->ul_ckg | +// p_rx_clk_opt->ul_start_sel | +// SSC_RCMR_PERIOD(p_rx_clk_opt->ul_period) | +// SSC_RCMR_STTDLY(p_rx_clk_opt->ul_sttdly); +// } + +// if (p_rx_data_frame == NULL) { +// p_ssc->SSC_RFMR = 0; +// } else { +// p_ssc->SSC_RFMR |= SSC_RFMR_DATLEN(p_rx_data_frame->ul_datlen) | +// p_rx_data_frame->ul_msbf | +// SSC_RFMR_DATNB(p_rx_data_frame->ul_datnb) | +// SSC_RFMR_FSLEN(p_rx_data_frame->ul_fslen) | +// SSC_RFMR_FSLEN_EXT(p_rx_data_frame->ul_fslen_ext) | +// p_rx_data_frame->ul_fsos | +// p_rx_data_frame->ul_fsedge; +// } +//} + +/** + * \brief Configure SSC transmitter clock mode and date frame configuration. + * + * \param p_ssc Pointer to an SSC instance. + * \param p_tx_clk_opt Pointer to the transmitter clock configuration structure. + * \param p_tx_data_frame Pointer to the transmitter data frame configuration structure. + */ +//void ssc_set_transmitter(Ssc *p_ssc, clock_opt_t *p_tx_clk_opt, +// data_frame_opt_t *p_tx_data_frame) +//{ +// if (p_tx_clk_opt == NULL) { +// p_ssc->SSC_TCMR = 0; +// } else { +// p_ssc->SSC_TCMR |= p_tx_clk_opt->ul_cks | +// p_tx_clk_opt->ul_cko | p_tx_clk_opt->ul_cki | +// p_tx_clk_opt->ul_ckg | +// p_tx_clk_opt->ul_start_sel | +// SSC_RCMR_PERIOD(p_tx_clk_opt->ul_period) | +// SSC_RCMR_STTDLY(p_tx_clk_opt->ul_sttdly); +// } + +// if (p_tx_data_frame == NULL) { +// p_ssc->SSC_TFMR = 0; +// } else { +// p_ssc->SSC_TFMR |= SSC_RFMR_DATLEN(p_tx_data_frame->ul_datlen) | +// p_tx_data_frame->ul_msbf | +// SSC_RFMR_DATNB(p_tx_data_frame->ul_datnb) | +// SSC_RFMR_FSLEN(p_tx_data_frame->ul_fslen) | +// SSC_RFMR_FSLEN_EXT(p_tx_data_frame->ul_fslen_ext) | +// p_tx_data_frame->ul_fsos | +// p_tx_data_frame->ul_fsedge; +// } +//} + +/** + * \brief Configure SSC Receive Compare Register. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_id Compare register ID. + * \param ul_value Value to configure. + */ +//void ssc_set_rx_compare(Ssc *p_ssc, uint32_t ul_id, uint32_t ul_value) +//{ +// switch (ul_id) { +/// case COMPARE_ID0: +// p_ssc->SSC_RC0R = ul_value; +// break; +// case COMPARE_ID1: +// p_ssc->SSC_RC1R = ul_value; +// break; +// } +//} + +/** + * \brief Get SSC Receive Compare Register. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_id Compare register ID. + * + * \return Receive Compare Register value for the specified ul_id, otherwise SSC_RC_INVALID. + */ +//uint32_t ssc_get_rx_compare(Ssc *p_ssc, uint32_t ul_id) +//{ +// switch (ul_id) { +// case COMPARE_ID0: +// return p_ssc->SSC_RC0R; +// case COMPARE_ID1: +// return p_ssc->SSC_RC1R; +// default: +// return SSC_RC_INVALID; +// } +//} + +/** + * \brief Enable SSC interrupts. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_sources Interrupts to be enabled. + */ +void ssc_enable_interrupt(Ssc *p_ssc, uint32_t ul_sources) +{ + p_ssc->SSC_IER = ul_sources; +} + +/** + * \brief Disable SSC interrupts. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_sources Interrupts to be enabled. + */ +void ssc_disable_interrupt(Ssc *p_ssc, uint32_t ul_sources) +{ + p_ssc->SSC_IDR = ul_sources; +} + +/** + * \brief Read SSC interrupt mask. + * + * \param p_ssc Pointer to an SSC instance. + * + * \return The interrupt mask value. + */ +uint32_t ssc_get_interrupt_mask(Ssc *p_ssc) +{ + return p_ssc->SSC_IMR; +} + +/** + * \brief Read SSC status. + * + * \param p_ssc Pointer to an SSC instance. + * + * \return The SSC status value. + */ +RAMFUNC +uint32_t ssc_get_status(Ssc *p_ssc) +{ + return p_ssc->SSC_SR; +} + +/** + * \brief Check if data has been loaded in SSC_THR and is waiting to be loaded + * in the Transmit Shift Register (TSR). + * + * \param p_ssc Pointer to an SSC instance. + * + * \retval SSC_RC_YES There is no data in the SSC_THR. + * \retval SSC_RC_NO There is one data in the SSC_THR. + */ +//uint32_t ssc_is_tx_ready(Ssc *p_ssc) +//{ +// if (p_ssc->SSC_SR & SSC_SR_TXRDY) { +// return SSC_RC_YES; +// } +// return SSC_RC_NO; +//} + +/** + * \brief Check if the last data written in SSC_THR has been loaded in TSR + * and the last data loaded in TSR has been transmitted. + * + * \param p_ssc Pointer to an SSC instance. + * + * \retval SSC_RC_YES Both of the two registers are empty. + * \retval SSC_RC_NO At least one of the two registers is not empty. + */ +//uint32_t ssc_is_tx_empty(Ssc *p_ssc) +//{ +// if (p_ssc->SSC_SR & SSC_SR_TXEMPTY) { +// return SSC_RC_YES; +// } +// return SSC_RC_NO; +//} + +/** + * \brief Check if data has been received and loaded in SSC_RHR. + * + * \param p_ssc Pointer to an SSC instance. + * + * \retval SSC_RC_YES There is one data in the SSC_RHR. + * \retval SSC_RC_NO There is no data in the SSC_RHR. + */ +//uint32_t ssc_is_rx_ready(Ssc *p_ssc) +//{ +// if (p_ssc->SSC_SR & SSC_SR_RXRDY) { +// return SSC_RC_YES; +// } +// return SSC_RC_NO; +//} + +/** + * \brief Check if transmitter is enabled. + * + * \param p_ssc Pointer to an SSC instance. + * + * \retval SSC_RC_YES The transmitter is enabled. + * \retval SSC_RC_NO The transmitter is disabled. + */ +uint32_t ssc_is_tx_enabled(Ssc *p_ssc) +{ + if (p_ssc->SSC_SR & SSC_SR_TXEN) { + return SSC_RC_YES; + } + return SSC_RC_NO; +} + +/** + * \brief Check if receiver is enabled. + * + * \param p_ssc Pointer to an SSC instance. + * + * \retval SSC_RC_YES The receiver is enabled. + * \retval SSC_RC_NO The receiver is disabled. + */ +uint32_t ssc_is_rx_enabled(Ssc *p_ssc) +{ + if (p_ssc->SSC_SR & SSC_SR_RXEN) { + return SSC_RC_YES; + } + return SSC_RC_NO; +} + +#if SAM3S || SAM4S +/** + * \brief Check if one receive buffer is filled. + * + * \param p_ssc Pointer to an SSC instance. + * + * \retval SSC_RC_YES Receive Counter has reached zero. + * \retval SSC_RC_NO Data is written on the Receive Counter Register or + * Receive Next Counter Register. + */ +//uint32_t ssc_is_rx_buf_end(Ssc *p_ssc) +//{ +// if (p_ssc->SSC_SR & SSC_SR_ENDRX) { +// return SSC_RC_YES; +// } +// return SSC_RC_NO; +//} + +/** + * \brief Check if the register SSC_TCR has reached 0. + * + * \param p_ssc Pointer to an SSC instance. + * + * \retval SSC_RC_YES The register SSC_TCR has reached 0. + * \retval SSC_RC_NO The register SSC_TCR hasn't reached 0. + */ +//uint32_t ssc_is_tx_buf_end(Ssc *p_ssc) +//{ +// if (p_ssc->SSC_SR & SSC_SR_ENDTX) { +// return SSC_RC_YES; +// } +// return SSC_RC_NO; +//} + +/** + * \brief Check if both receive buffers are full. + * + * \param p_ssc Pointer to an SSC instance. + * + * \retval SSC_RC_YES Both of the two receive buffers have reached 0. + * \retval SSC_RC_NO One of the two receive buffers hasn't reached 0. + */ +//uint32_t ssc_is_rx_buf_full(Ssc *p_ssc) +//{ +// if (p_ssc->SSC_SR & SSC_SR_RXBUFF) { +// return SSC_RC_YES; +// } +// return SSC_RC_NO; +//} + +/** + * \brief Check if both transmit buffers are empty. + * + * \param p_ssc Pointer to an SSC instance. + * + * \retval SSC_RC_YES Both of the two transmit buffers have reached 0. + * \retval SSC_RC_NO One of the two transmit buffers hasn't reached 0. + */ +//uint32_t ssc_is_tx_buf_empty(Ssc *p_ssc) +//{ +// if (p_ssc->SSC_SR & SSC_SR_TXBUFE) { +// return SSC_RC_YES; +// } +// return SSC_RC_NO; +//} + +/** + * \brief Get SSC PDC registers base address. + * + * \param p_ssc Pointer to SSC registers set instance. + * + * \return SSC PDC registers base address for PDC driver to access. + */ +//Pdc *ssc_get_pdc_base(Ssc *p_ssc) +//{ +// return (Pdc *)&(p_ssc->SSC_RPR); +//} +#endif + + + +//------------------------------------------------------------------------------ +/// Sends one data frame through a SSC peripheral. If another frame is currently +/// being sent, this function waits for the previous transfer to complete. +/// \param ssc Pointer to an SSC instance. +/// \param frame Data frame to send. +//------------------------------------------------------------------------------ +void SSC_Write(Ssc *ssc, unsigned int frame) +{ + while ((ssc->SSC_SR & SSC_SR_TXRDY) == 0); + ssc->SSC_THR = frame; +} + +//------------------------------------------------------------------------------ +/// Sends the contents of a data buffer a SSC peripheral, using the PDC. Returns +/// true if the buffer has been queued for transmission; otherwise returns +/// false. +/// \param ssc Pointer to an SSC instance. +/// \param buffer Data buffer to send. +/// \param length Size of the data buffer. +//------------------------------------------------------------------------------ +RAMFUNC +uint32_t SSC_WriteBuffer(Ssc *ssc,uint32_t buffer,uint32_t length) +{ + // Check if first bank is free + if (ssc->SSC_TCR == 0) { + + ssc->SSC_TPR = (uint32_t) buffer; + ssc->SSC_TCR = length; + ssc->SSC_PTCR = PERIPH_PTCR_TXTEN; + return 0; + } + // Check if second bank is free + else if (ssc->SSC_TNCR == 0) { + + ssc->SSC_TNPR = (uint32_t) buffer; + ssc->SSC_TNCR = length; + return 0; + } + + // No free banks + return 1; +} + +//------------------------------------------------------------------------------ +/// Waits until one frame is received on a SSC peripheral, and returns it. +/// \param ssc Pointer to an AT91S_SSC instance. +//------------------------------------------------------------------------------ +//void SSC_Read(Ssc *ssc) +//{ + //while ((ssc->SSC_SR & SSC_SR_RXRDY) == 0); + //return ssc->SSC_RHR; +//} + +//------------------------------------------------------------------------------ +/// Reads data coming from a SSC peripheral receiver and stores it into the +/// provided buffer. Returns true if the buffer has been queued for reception; +/// otherwise returns false. +/// \param ssc Pointer to an AT91S_SSC instance. +/// \param buffer Data buffer used for reception. +/// \param length Size in bytes of the data buffer. +//------------------------------------------------------------------------------ +RAMFUNC +uint32_t SSC_ReadBuffer(Ssc *ssc,uint32_t buffer,uint32_t length) +{ + // Check if the first bank is free + if (ssc->SSC_RCR == 0) { + + ssc->SSC_RPR =(uint32_t)buffer; + ssc->SSC_RCR = length; + ssc->SSC_PTCR = PERIPH_PTCR_RXTEN; + return 0; + } + // Check if second bank is free + else if (ssc->SSC_RNCR == 0) { + + ssc->SSC_RNPR = (uint32_t) buffer; + ssc->SSC_RNCR = length; + return 0; + } + + // No free bank + return 1; +} + +/** + * \brief Write to SSC Transmit Holding Register. + * Send data through SSC Data frame. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_frame Frame data to be transmitted. + * + * \retval SSC_RC_ERROR Time-out. + * \retval SSC_RC_OK Success. + * + */ +//uint32_t ssc_write(Ssc *p_ssc, uint32_t ul_frame) +////{ + // ul_timeout = SSC_DEFAULT_TIMEOUT; + + //while (!(p_ssc->SSC_SR & SSC_SR_TXEMPTY)) { + //if (!ul_timeout--) { + //return SSC_RC_ERROR; + //} + //} + +// p_ssc->SSC_THR = ul_frame; +// return SSC_RC_OK; +//} + +/** + * \brief Read from SSC Receive Holding Register. + * Read data that is received in SSC Data frame. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_data Pointer to the location where to store the received data. + * + * \retval SSC_RC_ERROR Time-out. + * \retval SSC_RC_OK Success. + */ +//uint32_t ssc_read(Ssc *p_ssc, uint32_t *ul_data) +//{ +// uint32_t ul_timeout = SSC_DEFAULT_TIMEOUT; + +// while (!(p_ssc->SSC_SR & SSC_SR_RXRDY)) { +// if (!ul_timeout--) { +// return SSC_RC_ERROR; +// } +// } + +// *ul_data = p_ssc->SSC_RHR; +// return SSC_RC_OK; +//} + +/** + * \brief Write to SSC Transmit Synchronization Holding Register. + * Send data through SSC Synchronization frame. If there is sync data that needs to be + * transmitted, call this function first to send out the sync data, and then call the + * ssc_write() function to send out application data. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_frame Frame Synchronization data. + */ +//void ssc_write_sync_data(Ssc *p_ssc, uint32_t ul_frame) +//{ +// p_ssc->SSC_TSHR = ul_frame; +//} + +/** + * \brief Read from SSC Receive Synchronization Holding Register. + * Read data that is received in SSC Synchronization frame. When the sync data is actually + * used, after successfully reading the application data by calling ssc_read(), call + * this function, and the return sync data is useful. + * + * \param p_ssc Pointer to an SSC instance. + * + * \return Current RSHR value. + */ +//uint32_t ssc_read_sync_data(Ssc *p_ssc) +//{ +// return p_ssc->SSC_RSHR; +//} + +//#if (SAM3XA || SAM3U) +/** + * \brief Get Transmit address for DMA operation. + * + * \param p_ssc Pointer to an SSC instance. + * + * \return Transmitting address for DMA access. + */ +//void *ssc_get_tx_access(Ssc *p_ssc) +//{ +// return (void *)&(p_ssc->SSC_THR); +//} + +/** + * \brief Get Receive address for DMA operation. + * + * \param p_ssc Pointer to an SSC instance. + * + * \return Transmitting address for DMA access. + */ +//void *ssc_get_rx_access(Ssc *p_ssc) +//{ +// return (void *)&(p_ssc->SSC_RHR); +//} +//#endif + +/** + * \brief Enable or disable write protection of SSC registers. + * + * \param p_ssc Pointer to an SSC instance. + * \param ul_enable 1 to enable, 0 to disable. + */ +void ssc_set_writeprotect(Ssc *p_ssc, uint32_t ul_enable) +{ + if (ul_enable) { + p_ssc->SSC_WPMR = SSC_WPKEY | SSC_WPMR_WPEN; + } else { + p_ssc->SSC_WPMR = SSC_WPKEY; + } +} + +/** + * \brief Indicate write protect status. + * + * \param p_ssc Pointer to an SSC instance. + * + * \return 0 if the peripheral is not protected. Write Protect Violation Status otherwise. + */ +uint32_t ssc_get_writeprotect_status(Ssc *p_ssc) +{ + uint32_t ul_reg_val; + + ul_reg_val = p_ssc->SSC_WPMR; + if (ul_reg_val & SSC_WPMR_WPEN) { + return (ul_reg_val & SSC_WPSR_WPVSRC_Msk) >> SSC_WPSR_WPVSRC_Pos; + } else { + return 0; + } +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/SAM3S4B/src/ASF/drivers1/ssc/ssc.h b/SAM3S4B/src/ASF/drivers1/ssc/ssc.h new file mode 100644 index 0000000..3fd2d45 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/ssc/ssc.h @@ -0,0 +1,218 @@ +/** + * \file + * + * \brief Synchronous Serial Controller (SSC) driver for SAM. + * + * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef SSC_H_INCLUDED +#define SSC_H_INCLUDED + +#include "compiler.h" +#include "XNL.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +//! Receive stop selection. +#define SSC_RX_STOP_COMPARE_0 0 +#define SSC_RX_STOP_COMPARE_0_1 1 + +//! Compare register ID. +#define COMPARE_ID0 0 +#define COMPARE_ID1 1 + +//! SSC module default timeout. */ +#define SSC_DEFAULT_TIMEOUT 10000 + +//! \brief SSC driver return codes. +enum ssc_return_code { + SSC_RC_OK = 0, //!< OK + SSC_RC_YES = 0, //!< Yes + SSC_RC_NO = 1, //!< No + SSC_RC_ERROR = 1, //!< General error + SSC_RC_INVALID = 0xFFFFFFFF //!< Parameter invalid +}; +/* +//! Data frame structure. +typedef struct { + //! Data bits length per transfer, should be 0 to 31. + uint32_t ul_datlen; + //! Bit sequence LSBF or MSBF. + //! For receiver configuration, SSC_RFMR_MSBF or 0. + //! For transmitter configuration, SSC_TFMR_MSBF or 0. + uint32_t ul_msbf; + //! Data number per frame, should be 0 to 15. + uint32_t ul_datnb; + //! Frame Sync. length should be 0 to 15. + uint32_t ul_fslen; + //! Frame Sync. length extension field, should be 0 to 15. + uint32_t ul_fslen_ext; + //! Frame Sync. output selection. + //! For receiver configuration, one of SSC_RFMR_FSOS_NONE, SSC_RFMR_FSOS_NEGATIVE, SSC_RFMR_FSOS_POSITIVE, + //! SSC_RFMR_FSOS_LOW, SSC_RFMR_FSOS_HIGH or SSC_RFMR_FSOS_TOGGLING. + //! For transmitter configuration, one of SSC_TFMR_FSOS_NONE, SSC_TFMR_FSOS_NEGATIVE, SSC_TFMR_FSOS_POSITIVE + //! SSC_TFMR_FSOS_LOW, SSC_TFMR_FSOS_HIGH, SSC_TFMR_FSOS_TOGGLING, + uint32_t ul_fsos; + //! Frame Sync. edge detection. + //! For receiver configuration, SSC_RFMR_FSEDGE_POSITIVE or SSC_RFMR_FSEDGE_NEGATIVE. + //! For transmitter configuration, SSC_TFMR_FSEDGE_POSITIVE or SSC_TFMR_FSEDGE_NEGATIVE. + uint32_t ul_fsedge; +} data_frame_opt_t; + +//! Clock mode structure. +typedef struct { + //! Communication clock selection. + //! For receiver configuration, one of SSC_RCMR_CKS_MCK, SSC_RCMR_CKS_TK or SSC_RCMR_CKS_RK. + //! For transmitter configuration, one of SSC_TCMR_CKS_MCK, SSC_TCMR_CKS_TK or SSC_TCMR_CKS_RK. + uint32_t ul_cks; + //! Communication clock output mode selection. + //! For receiver configuration, one of SSC_RCMR_CKO_NONE, SSC_RCMR_CKO_CONTINUOUS or SSC_RCMR_CKO_TRANSFER. + //! For transmitter configuration, one of SSC_TCMR_CKO_NONE, SSC_TCMR_CKO_CONTINUOUS or SSC_TCMR_CKO_TRANSFER. + uint32_t ul_cko; + //! Communication clock inversion. + //! For receiver configuration, SSC_RCMR_CKI or 0. + //! For transmitter configuration, SSC_TCMR_CKI or 0. + uint32_t ul_cki; + //! Communication clock gating selection. + //! For receiver configuration, one of SSC_RCMR_CKG_NONE, SSC_RCMR_CKG_CONTINUOUS and SSC_RCMR_CKG_TRANSFER. + //! For transmitter configuration, one of SSC_TCMR_CKG_NONE, SSC_TCMR_CKG_CONTINUOUS and SSC_TCMR_CKG_TRANSFER. + uint32_t ul_ckg; + //! Period divider selection, should be 0 to 255. + uint32_t ul_period; + //! Communication start delay, should be 0 to 255. + uint32_t ul_sttdly; + //! Communication start selection. + //! For receiver configuration, one of SSC_RCMR_START_CONTINUOUS, SSC_RCMR_START_TRANSMIT, SSC_RCMR_START_RF_LOW, + //! SSC_RCMR_START_RF_HIGH, SSC_RCMR_START_RF_FALLING, SSC_RCMR_START_RF_RISING, SSC_RCMR_START_RF_LEVEL, + //! SSC_RCMR_START_RF_EDGE or SSC_RCMR_START_CMP_0. + //! For transmitter configuration, one of SSC_TCMR_START_CONTINUOUS, SSC_TCMR_START_TRANSMIT, SSC_TCMR_START_RF_LOW, + //! SSC_TCMR_START_RF_HIGH, SSC_TCMR_START_RF_FALLING, SSC_TCMR_START_RF_RISING, SSC_TCMR_START_RF_LEVEL, + //! SSC_TCMR_START_RF_EDGE or SSC_TCMR_START_CMP_0. + uint32_t ul_start_sel; +} clock_opt_t; + +//! SSC working role in I2S mode. +#define SSC_I2S_MASTER_OUT (1 << 0) //! Working mode for transmitter as master. +#define SSC_I2S_MASTER_IN (1 << 1) //! Working mode for receiver as master. +#define SSC_I2S_SLAVE_OUT (1 << 2) //! Working mode for transmitter as slave. +#define SSC_I2S_SLAVE_IN (1 << 3) //! Working mode for receiver as slave. + +//! Bit for SSC Audio channel left. +#define SSC_AUDIO_CH_LEFT (1 << 0) +//! Bit for SSC Audio channel right. +#define SSC_AUDIO_CH_RIGHT (1 << 1) +//! SSC Audio Channel modes. +enum { + //! Mono, left channel enabled. + SSC_AUDIO_MONO_LEFT = (SSC_AUDIO_CH_LEFT), + //! Mono, right channel enabled. + SSC_AUDIO_MONO_RIGHT = (SSC_AUDIO_CH_RIGHT), + //! Stereo, two channels. + SSC_AUDIO_STERO = (SSC_AUDIO_CH_LEFT | SSC_AUDIO_CH_RIGHT) +}; +*/ + +void SSC_Write(Ssc *ssc, unsigned int frame); +extern uint32_t SSC_WriteBuffer(Ssc *ssc,uint32_t buffer,uint32_t length); +void SSC_Read(Ssc *ssc); +extern uint32_t SSC_ReadBuffer(Ssc *ssc,uint32_t buffer,uint32_t length); + + +uint32_t ssc_set_clock_divider(Ssc *p_ssc, uint32_t ul_bitclock, uint32_t ul_mck); +//void ssc_i2s_set_transmitter(Ssc *p_ssc, uint32_t ul_mode, +// uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen); +//void ssc_i2s_set_receiver(Ssc *p_ssc, uint32_t ul_mode, +// uint32_t ul_cks, uint32_t ul_ch_mode, uint32_t ul_datlen); +void ssc_reset(Ssc *p_ssc); +void ssc_enable_rx(Ssc *p_ssc); +void ssc_disable_rx(Ssc *p_ssc); +void ssc_enable_tx(Ssc *p_ssc); +void ssc_disable_tx(Ssc *p_ssc); +void ssc_set_normal_mode(Ssc *p_ssc); +//void ssc_set_loop_mode(Ssc *p_ssc); +void ssc_set_rx_stop_selection(Ssc *p_ssc, uint32_t ul_sel); +void ssc_set_td_default_level(Ssc *p_ssc, uint32_t ul_level); +void ssc_enable_tx_frame_sync_data(Ssc *p_ssc); +void ssc_disable_tx_frame_sync_data(Ssc *p_ssc); +//void ssc_set_receiver(Ssc *p_ssc, clock_opt_t *p_rx_clk_opt, data_frame_opt_t *p_rx_data_frame); +//void ssc_set_transmitter(Ssc *p_ssc, clock_opt_t *p_tx_clk_opt, data_frame_opt_t *p_tx_data_frame); +//void ssc_set_rx_compare(Ssc *p_ssc, uint32_t ul_id, uint32_t ul_value); +//uint32_t ssc_get_rx_compare(Ssc *p_ssc, uint32_t ul_id); +void ssc_enable_interrupt(Ssc *p_ssc, uint32_t ul_sources); +void ssc_disable_interrupt(Ssc *p_ssc, uint32_t ul_sources); +uint32_t ssc_get_interrupt_mask(Ssc *p_ssc); +uint32_t ssc_get_status(Ssc *p_ssc); +//uint32_t ssc_is_tx_ready(Ssc *p_ssc); +//uint32_t ssc_is_tx_empty(Ssc *p_ssc); +//uint32_t ssc_is_rx_ready(Ssc *p_ssc); +uint32_t ssc_is_tx_enabled(Ssc *p_ssc); +uint32_t ssc_is_rx_enabled(Ssc *p_ssc); +#if SAM3S || SAM4S +uint32_t ssc_is_rx_buf_end(Ssc *p_ssc); +uint32_t ssc_is_tx_buf_end(Ssc *p_ssc); +uint32_t ssc_is_rx_buf_full(Ssc *p_ssc); +uint32_t ssc_is_tx_buf_empty(Ssc *p_ssc); +Pdc *ssc_get_pdc_base(Ssc *p_ssc); +#endif +uint32_t ssc_write(Ssc *p_ssc, uint32_t ul_frame); +uint32_t ssc_read(Ssc *p_ssc, uint32_t *ul_data); +void ssc_write_sync_data(Ssc *p_ssc, uint32_t ul_frame); +uint32_t ssc_read_sync_data(Ssc *p_ssc); +#if (SAM3XA || SAM3U) +void *ssc_get_tx_access(Ssc *p_ssc); +void *ssc_get_rx_access(Ssc *p_ssc); +#endif +void ssc_set_writeprotect(Ssc *p_ssc, uint32_t ul_enable); +uint32_t ssc_get_writeprotect_status(Ssc *p_ssc); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* SSC_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/timer/tc.c b/SAM3S4B/src/ASF/drivers1/timer/tc.c new file mode 100644 index 0000000..8e8c5a9 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/timer/tc.c @@ -0,0 +1,597 @@ +/** + * \file + * + * \brief Timer Counter (TC) driver for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include "tc.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +#define TC_WPMR_WPKEY_VALUE TC_WPMR_WPKEY((uint32_t)0x54494D) + +/** + * \defgroup sam_drivers_tc_group Timer Counter (TC) + * + * The Timer Counter (TC) includes three identical 32-bit Timer Counter + * channels. Each channel can be independently programmed to perform a wide + * range of functions including frequency measurement, event counting, + * interval measurement, pulse generation, delay timing and pulse width + * modulation. + * + * @{ + */ + +/** + * \brief Configure TC for timer, waveform generation or capture. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * \param ul_mode Control mode register value to set. + * + * \attention If the TC is configured for waveform generation, the external + * event selection (EEVT) should only be set to \c TC_CMR_EEVT_TIOB or the + * equivalent value \c 0 if it really is the intention to use TIOB as an + * external event trigger.\n + * This is because the setting forces TIOB to be an input even if the + * external event trigger has not been enabled with \c TC_CMR_ENETRG, and + * thus prevents normal operation of TIOB. + */ +void tc_init(Tc *p_tc, uint32_t ul_channel, uint32_t ul_mode) +{ + TcChannel *tc_channel; + + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + tc_channel = p_tc->TC_CHANNEL + ul_channel; + + /* Disable TC clock. */ + tc_channel->TC_CCR = TC_CCR_CLKDIS; + + /* Disable interrupts. */ + tc_channel->TC_IDR = 0xFFFFFFFF; + + /* Clear status register. */ + tc_channel->TC_SR; + + /* Set mode. */ + tc_channel->TC_CMR = ul_mode; +} + +/** + * \brief Asserts a SYNC signal to generate a software trigger to + * all channels. + * + * \param p_tc Pointer to a TC instance. + * + */ +void tc_sync_trigger(Tc *p_tc) +{ + p_tc->TC_BCR = TC_BCR_SYNC; +} + +/** + * \brief Configure TC Block mode. + * \note tc_init() must be called first. + * + * \param p_tc Pointer to a TC instance. + * \param ul_blockmode Block mode register value to set. + * + */ +void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode) +{ + p_tc->TC_BMR = ul_blockmode; +} + +#if (!SAM3U) + +/** + * \brief Configure TC for 2-bit Gray Counter for Stepper Motor. + * \note tc_init() must be called first. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * \param ul_steppermode Stepper motor mode register value to set. + * + * \return 0 for OK. + */ +uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_steppermode) +{ + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_SMMR = ul_steppermode; + return 0; +} + +#endif + +/** + * \brief Start TC clock counter on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + */ +void tc_start(Tc *p_tc, uint32_t ul_channel) +{ + //Assert(ul_channel < + //(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG; +} + +/** + * \brief Stop TC clock counter on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + */ +void tc_stop(Tc *p_tc, uint32_t ul_channel) +{ + //Assert(ul_channel < + //(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_CCR = TC_CCR_CLKDIS; +} + +/** + * \brief Read counter value on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * + * \return Counter value. + */ +uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel) +{ + //Assert(ul_channel < + // (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + return p_tc->TC_CHANNEL[ul_channel].TC_CV; +} + +/** + * \brief Read RA TC counter on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * + * \return RA value. + */ +uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel) +{ + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + return p_tc->TC_CHANNEL[ul_channel].TC_RA; +} + +/** + * \brief Read RB TC counter on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * + * \return RB value. + */ +uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel) +{ + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + return p_tc->TC_CHANNEL[ul_channel].TC_RB; +} + +/** + * \brief Read RC TC counter on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * + * \return RC value. + */ +uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel) +{ + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + return p_tc->TC_CHANNEL[ul_channel].TC_RC; +} + +/** + * \brief Write RA TC counter on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * \param ul_value Value to set in register. + */ +void tc_write_ra(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_value) +{ + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_RA = ul_value; +} + +/** + * \brief Write RB TC counter on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * \param ul_value Value to set in register. + */ +void tc_write_rb(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_value) +{ + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_RB = ul_value; +} + +/** + * \brief Write RC TC counter on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * \param ul_value Value to set in register. + */ +void tc_write_rc(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_value) +{ + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + + p_tc->TC_CHANNEL[ul_channel].TC_RC = ul_value; +} + +/** + * \brief Enable TC interrupts on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * \param ul_sources Interrupt sources bit map. + */ +void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_sources) +{ + TcChannel *tc_channel; + + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + tc_channel = p_tc->TC_CHANNEL + ul_channel; + tc_channel->TC_IER = ul_sources; +} + +/** + * \brief Disable TC interrupts on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * \param ul_sources Interrupt sources bit map. + */ +void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_sources) +{ + TcChannel *tc_channel; + + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + tc_channel = p_tc->TC_CHANNEL + ul_channel; + tc_channel->TC_IDR = ul_sources; +} + +/** + * \brief Read TC interrupt mask on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * + * \return The interrupt mask value. + */ +uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel) +{ + TcChannel *tc_channel; + + Assert(ul_channel < + (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + tc_channel = p_tc->TC_CHANNEL + ul_channel; + return tc_channel->TC_IMR; +} + +/** + * \brief Get current status on the selected channel. + * + * \param p_tc Pointer to a TC instance. + * \param ul_channel Channel to configure. + * + * \return The current TC status. + */ +//RAMFUNC +uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel) +{ + TcChannel *tc_channel; + + //Assert(ul_channel < + //(sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0]))); + tc_channel = p_tc->TC_CHANNEL + ul_channel; + return tc_channel->TC_SR; +} + +/* TC divisor used to find the lowest acceptable timer frequency */ +#define TC_DIV_FACTOR 65536 + +#if (!SAM4L) + +#ifndef FREQ_SLOW_CLOCK_EXT +#define FREQ_SLOW_CLOCK_EXT 32768 /* External slow clock frequency (hz) */ +#endif + +/** + * \brief Find the best MCK divisor. + * + * Finds the best MCK divisor given the timer frequency and MCK. The result + * is guaranteed to satisfy the following equation: + * \code + * (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) + * \endcode + * with DIV being the lowest possible value, + * to maximize timing adjust resolution. + * + * \param ul_freq Desired timer frequency. + * \param ul_mck Master clock frequency. + * \param p_uldiv Divisor value. + * \param p_ultcclks TCCLKS field value for divisor. + * \param ul_boardmck Board clock frequency. + * + * \return 1 if a proper divisor has been found, otherwise 0. + */ +uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, + uint32_t *p_uldiv, uint32_t *p_ultcclks, uint32_t ul_boardmck) +{ + const uint32_t divisors[7] = { 2, 8, 32, 128, 512, 1024, + ul_boardmck / FREQ_SLOW_CLOCK_EXT }; + uint32_t ul_index; + uint32_t ul_high, ul_low; + + /* Satisfy frequency bound. */ + for (ul_index = 0; + ul_index < (sizeof(divisors) / sizeof(divisors[0])); + ul_index++) { + ul_high = ul_mck / divisors[ul_index]; + ul_low = ul_high / TC_DIV_FACTOR; + if (ul_freq > ul_high) { + return 0; + } else if (ul_freq >= ul_low) { + break; + } + } + if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) { + return 0; + } + + /* Store results. */ + if (p_uldiv) { + *p_uldiv = divisors[ul_index]; + } + + if (p_ultcclks) { + *p_ultcclks = ul_index; + } + + return 1; +} + +#endif + +#if (SAM4L) +/** + * \brief Find the best PBA clock divisor. + * + * Finds the best divisor given the timer frequency and PBA clock. The result + * is guaranteed to satisfy the following equation: + * \code + * (ul_pbaclk / (2* DIV * 65536)) <= freq <= (ul_pbaclk / (2* DIV)) + * \endcode + * with DIV being the lowest possible value, + * to maximize timing adjust resolution. + * + * \param ul_freq Desired timer frequency. + * \param ul_mck PBA clock frequency. + * \param p_uldiv Divisor value. + * \param p_ultcclks TCCLKS field value for divisor. + * \param ul_boardmck useless here. + * + * \return 1 if a proper divisor has been found, otherwise 0. + */ +uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, + uint32_t *p_uldiv, uint32_t *p_ultcclks, uint32_t ul_boardmck) +{ + const uint32_t divisors[5] = { 0, 2, 8, 32, 128, 512}; + uint32_t ul_index; + uint32_t ul_high, ul_low; + + UNUSED(ul_boardmck); + + /* Satisfy frequency bound. */ + for (ul_index = 1; + ul_index < (sizeof(divisors) / sizeof(divisors[0])); + ul_index++) { + ul_high = ul_mck / divisors[ul_index]; + ul_low = ul_high / TC_DIV_FACTOR; + if (ul_freq > ul_high) { + return 0; + } else if (ul_freq >= ul_low) { + break; + } + } + if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) { + return 0; + } + + /* Store results. */ + if (p_uldiv) { + *p_uldiv = divisors[ul_index]; + } + + if (p_ultcclks) { + *p_ultcclks = ul_index; + } + + return 1; +} + +#endif + +#if (!SAM4L) + +/** + * \brief Enable TC QDEC interrupts. + * + * \param p_tc Pointer to a TC instance. + * \param ul_sources Interrupts to be enabled. + */ +void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources) +{ + p_tc->TC_QIER = ul_sources; +} + +/** + * \brief Disable TC QDEC interrupts. + * + * \param p_tc Pointer to a TC instance. + * \param ul_sources Interrupts to be disabled. + */ +void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources) +{ + p_tc->TC_QIDR = ul_sources; +} + +/** + * \brief Read TC QDEC interrupt mask. + * + * \param p_tc Pointer to a TC instance. + * + * \return The interrupt mask value. + */ +uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc) +{ + return p_tc->TC_QIMR; +} + +/** + * \brief Get current QDEC status. + * + * \param p_tc Pointer to a TC instance. + * + * \return The current TC status. + */ +uint32_t tc_get_qdec_interrupt_status(Tc *p_tc) +{ + return p_tc->TC_QISR; +} + +#endif + +#if (!SAM3U) + +/** + * \brief Enable or disable write protection of TC registers. + * + * \param p_tc Pointer to a TC instance. + * \param ul_enable 1 to enable, 0 to disable. + */ +void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable) +{ + if (ul_enable) { + p_tc->TC_WPMR = TC_WPMR_WPKEY_VALUE | TC_WPMR_WPEN; + } else { + p_tc->TC_WPMR = TC_WPMR_WPKEY_VALUE; + } +} + +#endif + +#if SAM4L + +/** + * \brief Indicate features. + * + * \param p_tc Pointer to a TC instance. + * + * \return TC_FEATURES value. + */ +uint32_t tc_get_feature(Tc *p_tc) +{ + return p_tc->TC_FEATURES; +} + +/** + * \brief Indicate version. + * + * \param p_tc Pointer to a TC instance. + * + * \return TC_VERSION value. + */ +uint32_t tc_get_version(Tc *p_tc) +{ + return p_tc->TC_VERSION; +} + +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/SAM3S4B/src/ASF/drivers1/timer/tc.h b/SAM3S4B/src/ASF/drivers1/timer/tc.h new file mode 100644 index 0000000..f69825b --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/timer/tc.h @@ -0,0 +1,114 @@ +/** + * \file + * + * \brief Timer Counter (TC) driver for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef TC_H_INCLUDED +#define TC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +void tc_init(Tc *p_tc, uint32_t ul_Channel, uint32_t ul_Mode); +void tc_sync_trigger(Tc *p_tc); +void tc_set_block_mode(Tc *p_tc, uint32_t ul_blockmode); + +#if (!SAM3U) +uint32_t tc_init_2bit_gray(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_steppermode); +#endif + +void tc_start(Tc *p_tc, uint32_t ul_channel); +void tc_stop(Tc *p_tc, uint32_t ul_channel); + +uint32_t tc_read_cv(Tc *p_tc, uint32_t ul_channel); +uint32_t tc_read_ra(Tc *p_tc, uint32_t ul_channel); +uint32_t tc_read_rb(Tc *p_tc, uint32_t ul_channel); +uint32_t tc_read_rc(Tc *p_tc, uint32_t ul_channel); + +void tc_write_ra(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_value); +void tc_write_rb(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_value); +void tc_write_rc(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_value); + +uint32_t tc_find_mck_divisor(uint32_t ul_freq, uint32_t ul_mck, + uint32_t *p_uldiv, uint32_t *ul_tcclks, uint32_t ul_boardmck); +void tc_enable_interrupt(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_sources); +void tc_disable_interrupt(Tc *p_tc, uint32_t ul_channel, + uint32_t ul_sources); +uint32_t tc_get_interrupt_mask(Tc *p_tc, uint32_t ul_channel); +uint32_t tc_get_status(Tc *p_tc, uint32_t ul_channel); +#if (!SAM4L) +void tc_enable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources); +void tc_disable_qdec_interrupt(Tc *p_tc, uint32_t ul_sources); +uint32_t tc_get_qdec_interrupt_mask(Tc *p_tc); +uint32_t tc_get_qdec_interrupt_status(Tc *p_tc); +#endif + +#if (!SAM3U) +void tc_set_writeprotect(Tc *p_tc, uint32_t ul_enable); +#endif + +#if SAM4L +uint32_t tc_get_feature(Tc *p_tc); +uint32_t tc_get_version(Tc *p_tc); + +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* TC_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/uart/uart.c b/SAM3S4B/src/ASF/drivers1/uart/uart.c new file mode 100644 index 0000000..86b9049 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/uart/uart.c @@ -0,0 +1,444 @@ +/** + * \file + * + * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "uart.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_uart_group Universal Asynchronous Receiver Transceiver (UART) + * + * The Universal Asynchronous Receiver Transmitter features a two-pin UART that + * can be used for communication and trace purposes and offers an ideal medium + * for in-situ programming solutions. Moreover, the association with two + * peripheral DMA controller (PDC) channels permits packet handling for these + * tasks with processor time reduced to a minimum. + * + * \par Usage + * + * -# Enable the UART peripheral clock in the PMC. + * -# Enable the required UART PIOs (see pio.h). + * -# Configure the UART by calling uart_init. + * -# Send data through the UART using the uart_write. + * -# Receive data from the UART using the uart_read; the availability of data + * can be polled with uart_is_rx_ready. + * -# Disable the transmitter and/or the receiver of the UART with + * uart_disable_tx and uart_disable_rx. + * + * @{ + */ + +/* UART internal div factor for sampling */ +#define UART_MCK_DIV 16 +/* Div factor to get the maximum baud rate */ +#define UART_MCK_DIV_MIN_FACTOR 1 +/* Div factor to get the minimum baud rate */ +#define UART_MCK_DIV_MAX_FACTOR 65535 + +/** + * \brief Configure UART with the specified parameters. + * + * \note The PMC and PIOs must be configured first. + * + * \param p_uart Pointer to a UART instance. + * \param p_uart_opt Pointer to sam_uart_opt_t instance. + * + * \retval 0 Success. + * \retval 1 Bad baud rate generator value. + */ +uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt) +{ + uint32_t cd = 0; + + /* Reset and disable receiver & transmitter */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; + + /* Check and configure baudrate */ + /* Asynchronous, no oversampling */ + cd = (p_uart_opt->ul_mck / p_uart_opt->ul_baudrate) / UART_MCK_DIV; + if (cd < UART_MCK_DIV_MIN_FACTOR || cd > UART_MCK_DIV_MAX_FACTOR) + return 1; + + p_uart->UART_BRGR = cd; + /* Configure mode */ + p_uart->UART_MR = p_uart_opt->ul_mode; + + /* Disable PDC channel */ + p_uart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; + + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; + + return 0; +} + +/** + * \brief Enable UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_tx(Uart *p_uart) +{ + /* Enable transmitter */ + p_uart->UART_CR = UART_CR_TXEN; +} + +/** + * \brief Disable UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_tx(Uart *p_uart) +{ + /* Disable transmitter */ + p_uart->UART_CR = UART_CR_TXDIS; +} + +/** + * \brief Reset UART transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_tx(Uart *p_uart) +{ + /* Reset transmitter */ + p_uart->UART_CR = UART_CR_RSTTX | UART_CR_TXDIS; +} + +/** + * \brief Enable UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable_rx(Uart *p_uart) +{ + /* Enable receiver */ + p_uart->UART_CR = UART_CR_RXEN; +} + +/** + * \brief Disable UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable_rx(Uart *p_uart) +{ + /* Disable receiver */ + p_uart->UART_CR = UART_CR_RXDIS; +} + +/** + * \brief Reset UART receiver. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset_rx(Uart *p_uart) +{ + /* Reset receiver */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RXDIS; +} + +/** + * \brief Enable UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_enable(Uart *p_uart) +{ + /* Enable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; +} + +/** + * \brief Disable UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_disable(Uart *p_uart) +{ + /* Disable receiver and transmitter */ + p_uart->UART_CR = UART_CR_RXDIS | UART_CR_TXDIS; +} + +/** + * \brief Reset UART receiver and transmitter. + * + * \param p_uart Pointer to a UART instance. + */ +void uart_reset(Uart *p_uart) +{ + /* Reset and disable receiver & transmitter */ + p_uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS; +} + +/** \brief Enable UART interrupts. + * + * \param p_uart Pointer to a UART instance. + * \param ul_sources Interrupts to be enabled. + */ +void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources) +{ + p_uart->UART_IER = ul_sources; +} + +/** \brief Disable UART interrupts. + * + * \param p_uart Pointer to a UART instance. + * \param ul_sources Interrupts to be disabled. + */ +void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources) +{ + p_uart->UART_IDR = ul_sources; +} + +/** \brief Read UART interrupt mask. + * + * \param p_uart Pointer to a UART instance. + * + * \return The interrupt mask value. + */ +uint32_t uart_get_interrupt_mask(Uart *p_uart) +{ + return p_uart->UART_IMR; +} + +/** + * \brief Get current status. + * + * \param p_uart Pointer to a UART instance. + * + * \return The current UART status. + */ +uint32_t uart_get_status(Uart *p_uart) +{ + return p_uart->UART_SR; +} + +/** + * \brief Check if Transmit is Ready. + * Check if data has been loaded in UART_THR and is waiting to be loaded in the + * Transmit Shift Register (TSR). + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Data has been transmitted. + * \retval 0 Transmit is not ready, data pending. + */ +uint32_t uart_is_tx_ready(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXRDY) > 0; +} + +/** + * \brief Check if Transmit Hold Register is empty. + * Check if the last data written in UART_THR has been loaded in TSR and the + * last data loaded in TSR has been transmitted. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmitter is empty. + * \retval 0 Transmitter is not empty. + */ +uint32_t uart_is_tx_empty(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0; +} + +/** + * \brief Check if Received data is ready. + * Check if data has been received and loaded in UART_RHR. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 One data has been received. + * \retval 0 No data has been received. + */ +uint32_t uart_is_rx_ready(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_RXRDY) > 0; +} + +/** + * \brief Check if one receive buffer is filled. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Receive is completed. + * \retval 0 Receive is still pending. + */ +uint32_t uart_is_rx_buf_end(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_ENDRX) > 0; +} + +/** + * \brief Check if one transmit buffer is sent out. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmit is completed. + * \retval 0 Transmit is still pending. + */ +uint32_t uart_is_tx_buf_end(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_ENDTX) > 0; +} + +/** + * \brief Check if both receive buffers are full. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Receive buffers are full. + * \retval 0 Receive buffers are not full. + */ +uint32_t uart_is_rx_buf_full(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_RXBUFF) > 0; +} + +/** + * \brief Check if both transmit buffers are sent out. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 1 Transmit buffer is empty. + * \retval 0 Transmit buffer is not empty. + */ +uint32_t uart_is_tx_buf_empty(Uart *p_uart) +{ + return (p_uart->UART_SR & UART_SR_TXEMPTY) > 0; +} + +/** + * \brief Write to UART Transmit Holding Register + * Before writing user should check if tx is ready (or empty). + * + * \param p_uart Pointer to a UART instance. + * \param data Data to be sent. + * + * \retval 0 Success. + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data) +{ + /* Check if the transmitter is ready */ + if (!(p_uart->UART_SR & UART_SR_TXRDY)) + return 1; + + /* Send character */ + p_uart->UART_THR = uc_data; + return 0; +} + +/** + * \brief Read from UART Receive Holding Register. + * Before reading user should check if rx is ready. + * + * \param p_uart Pointer to a UART instance. + * + * \retval 0 Success. + * \retval 1 I/O Failure, UART is not ready. + */ +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data) +{ + /* Check if the receiver is ready */ + if ((p_uart->UART_SR & UART_SR_RXRDY) == 0) + return 1; + + /* Read character */ + *puc_data = (uint8_t) p_uart->UART_RHR; + return 0; +} + +/** + * \brief Get UART PDC base address. + * + * \param p_uart Pointer to a UART instance. + * + * \return UART PDC registers base for PDC driver to access. + */ +Pdc *uart_get_pdc_base(Uart *p_uart) +{ + Pdc *p_pdc_base; + +#if (SAM3S || SAM3N || SAM4S || SAM4E || SAM4N) + if (p_uart == UART0) + p_pdc_base = PDC_UART0; +#elif (SAM3XA || SAM3U) + if (p_uart == UART) + p_pdc_base = PDC_UART; +#else +#error "Unsupported device" +#endif + +#if (SAM3S || SAM4S || SAM4E || SAM4N) + if (p_uart == UART1) + p_pdc_base = PDC_UART1; +#endif + +#if (SAM4N) + if (p_uart == UART2) + p_pdc_base = PDC_UART2; +#endif + + return p_pdc_base; +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/SAM3S4B/src/ASF/drivers1/uart/uart.h b/SAM3S4B/src/ASF/drivers1/uart/uart.h new file mode 100644 index 0000000..671a501 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/uart/uart.h @@ -0,0 +1,105 @@ +/** + * \file + * + * \brief Universal Asynchronous Receiver Transceiver (UART) driver for SAM. + * + * Copyright (c) 2011-2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef UART_H_INCLUDED +#define UART_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/*! \brief Option list for UART peripheral initialization */ +typedef struct sam_uart_opt { + /** MCK for UART */ + uint32_t ul_mck; + /** Expected baud rate */ + uint32_t ul_baudrate; + /** Initialize value for UART mode register */ + uint32_t ul_mode; + /** + * Configure channel mode (Normal, Automatic, Local_loopback or + * Remote_loopback) + */ + uint32_t ul_chmode; +} sam_uart_opt_t; + +uint32_t uart_init(Uart *p_uart, const sam_uart_opt_t *p_uart_opt); +void uart_enable_tx(Uart *p_uart); +void uart_disable_tx(Uart *p_uart); +void uart_reset_tx(Uart *p_uart); +void uart_enable_rx(Uart *p_uart); +void uart_disable_rx(Uart *p_uart); +void uart_reset_rx(Uart *p_uart); +void uart_enable(Uart *p_uart); +void uart_disable(Uart *p_uart); +void uart_reset(Uart *p_uart); +void uart_enable_interrupt(Uart *p_uart, uint32_t ul_sources); +void uart_disable_interrupt(Uart *p_uart, uint32_t ul_sources); +uint32_t uart_get_interrupt_mask(Uart *p_uart); +uint32_t uart_get_status(Uart *p_uart); +uint32_t uart_is_tx_ready(Uart *p_uart); +uint32_t uart_is_tx_empty(Uart *p_uart); +uint32_t uart_is_rx_ready(Uart *p_uart); +uint32_t uart_is_rx_buf_end(Uart *p_uart); +uint32_t uart_is_tx_buf_end(Uart *p_uart); +uint32_t uart_is_rx_buf_full(Uart *p_uart); +uint32_t uart_is_tx_buf_empty(Uart *p_uart); +uint32_t uart_write(Uart *p_uart, const uint8_t uc_data); +uint32_t uart_read(Uart *p_uart, uint8_t *puc_data); +Pdc *uart_get_pdc_base(Uart *p_uart); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* UART_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/usart/usart.c b/SAM3S4B/src/ASF/drivers1/usart/usart.c new file mode 100644 index 0000000..9fc5013 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/usart/usart.c @@ -0,0 +1,1756 @@ +/** + * \file + * + * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver + * for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "usart.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_usart_group Universal Synchronous Asynchronous + * Receiver Transmitter (USART) + * + * The Universal Synchronous Asynchronous Receiver Transceiver (USART) + * provides one full duplex universal synchronous asynchronous serial link. + * Data frame format is widely programmable (data length, parity, number of + * stop bits) to support a maximum of standards. The receiver implements + * parity error, framing error and overrun error detection. The receiver + * time-out enables handling variable-length frames and the transmitter + * timeguard facilitates communications with slow remote devices. Multidrop + * communications are also supported through address bit handling in reception + * and transmission. The driver supports the following modes: + * RS232, RS485, SPI, IrDA, ISO7816, MODEM, Hardware handshaking and LIN. + * + * @{ + */ + +/* The write protect key value. */ +#define US_WPKEY_VALUE 0x555341 + +/* The CD value scope programmed in MR register. */ +#define MIN_CD_VALUE 0x01 +#define MIN_CD_VALUE_SPI 0x04 +#define MAX_CD_VALUE US_BRGR_CD_Msk + +/* The receiver sampling divide of baudrate clock. */ +#define HIGH_FRQ_SAMPLE_DIV 16 +#define LOW_FRQ_SAMPLE_DIV 8 + +/* Max transmitter timeguard. */ +#define MAX_TRAN_GUARD_TIME US_TTGR_TG_Msk + +/* The non-existent parity error number. */ +#define USART_PARITY_ERROR 5 + +/* ISO7816 protocol type. */ +#define ISO7816_T_0 0 +#define ISO7816_T_1 1 + +/** + * \brief Calculate a clock divider(CD) and a fractional part (FP) for the + * USART asynchronous modes to generate a baudrate as close as possible to + * the baudrate set point. + * + * \note Baud rate calculation: Baudrate = ul_mck/(Over * (CD + FP/8)) + * (Over being 16 or 8). The maximal oversampling is selected if it allows to + * generate a baudrate close to the set point. + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_async_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t over; + uint32_t cd_fp; + uint32_t cd; + uint32_t fp; + + /* Calculate the receiver sampling divide of baudrate clock. */ + if (ul_mck >= HIGH_FRQ_SAMPLE_DIV * baudrate) { + over = HIGH_FRQ_SAMPLE_DIV; + } else { + over = LOW_FRQ_SAMPLE_DIV; + } + + /* Calculate clock divider according to the fraction calculated formula. */ + cd_fp = (8 * ul_mck + (over * baudrate) / 2) / (over * baudrate); + cd = cd_fp >> 3; + fp = cd_fp & 0x07; + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + /* Configure the OVER bit in MR register. */ + if (over == 8) { + p_usart->US_MR |= US_MR_OVER; + } + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = (cd << US_BRGR_CD_Pos) | (fp << US_BRGR_FP_Pos); + + return 0; +} + +/** + * \brief Calculate a clock divider for the USART synchronous master modes + * to generate a baudrate as close as possible to the baudrate set point. + * + * \note Synchronous baudrate calculation: baudrate = ul_mck / cd + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_sync_master_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate clock divider according to the formula in synchronous mode. */ + cd = (ul_mck + baudrate / 2) / baudrate; + + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | + US_MR_USCLKS_MCK | US_MR_SYNC; + return 0; +} + +/** + * \brief Select the SCK pin as the source of baud rate for the USART + * synchronous slave modes. + * + * \param p_usart Pointer to a USART instance. + */ +static void usart_set_sync_slave_baudrate(Usart *p_usart) +{ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USCLKS_Msk) | + US_MR_USCLKS_SCK | US_MR_SYNC; +} + + +/** + * \brief Calculate a clock divider (\e CD) for the USART ISO7816 mode to + * generate an ISO7816 clock as close as possible to the clock set point. + * + * \note ISO7816 clock calculation: Clock = ul_mck / cd + * + * \param p_usart Pointer to a USART instance. + * \param clock ISO7816 clock set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 ISO7816 clock is successfully initialized. + * \retval 1 ISO7816 clock set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_iso7816_clock(Usart *p_usart, + uint32_t clock, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate clock divider according to the formula in ISO7816 mode. */ + cd = (ul_mck + clock / 2) / clock; + + if (cd < MIN_CD_VALUE || cd > MAX_CD_VALUE) { + return 1; + } + + p_usart->US_MR = (p_usart->US_MR & ~(US_MR_USCLKS_Msk | US_MR_SYNC | + US_MR_OVER)) | US_MR_USCLKS_MCK | US_MR_CLKO; + + /* Configure the baudrate generate register. */ + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + return 0; +} + +/** + * \brief Calculate a clock divider (\e CD) for the USART SPI master mode to + * generate a baud rate as close as possible to the baud rate set point. + * + * \note Baud rate calculation: + * \f$ Baudrate = \frac{SelectedClock}{CD} \f$. + * + * \param p_usart Pointer to a USART instance. + * \param baudrate Baud rate set point. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 Baud rate is successfully initialized. + * \retval 1 Baud rate set point is out of range for the given input clock + * frequency. + */ +static uint32_t usart_set_spi_master_baudrate(Usart *p_usart, + uint32_t baudrate, uint32_t ul_mck) +{ + uint32_t cd; + + /* Calculate the clock divider according to the formula in SPI mode. */ + cd = (ul_mck + baudrate / 2) / baudrate; + + if (cd < MIN_CD_VALUE_SPI || cd > MAX_CD_VALUE) { + return 1; + } + + p_usart->US_BRGR = cd << US_BRGR_CD_Pos; + + return 0; +} + +/** + * \brief Select the SCK pin as the source of baudrate for the USART SPI slave + * mode. + * + * \param p_usart Pointer to a USART instance. + */ +static void usart_set_spi_slave_baudrate(Usart *p_usart) +{ + p_usart->US_MR &= ~US_MR_USCLKS_Msk; + p_usart->US_MR |= US_MR_USCLKS_SCK; +} + +/** + * \brief Reset the USART and disable TX and RX. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset(Usart *p_usart) +{ + /* Disable the Write Protect. */ + usart_disable_writeprotect(p_usart); + + /* Reset registers that could cause unpredictable behavior after reset. */ + p_usart->US_MR = 0; + p_usart->US_RTOR = 0; + p_usart->US_TTGR = 0; + + /* Disable TX and RX. */ + usart_reset_tx(p_usart); + usart_reset_rx(p_usart); + /* Reset status bits. */ + usart_reset_status(p_usart); + /* Turn off RTS and DTR if exist. */ + usart_drive_RTS_pin_high(p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + usart_drive_DTR_pin_high(p_usart); +#endif +} + +/** + * \brief Configure USART to work in RS232 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_rs232(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || usart_set_async_baudrate(p_usart, + p_usart_opt->baudrate, ul_mck)) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Configure the USART mode as normal mode. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL; + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in hardware handshaking mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_hw_handshaking(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set hardware handshaking mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_HW_HANDSHAKING; + + return 0; +} + +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + +/** + * \brief Configure USART to work in modem mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_modem(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* + * SAM3S, SAM4S and SAM4E series support MODEM mode only on USART1, + * SAM3U and SAM4L series support MODEM mode only on USART0. + */ +#if (SAM3S || SAM4S || SAM4E) + if (p_usart != USART0) { + return 1; + } +#elif (SAM3U || SAM4L) + if (p_usart != USART0) { + return 1; + } +#endif + + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set MODEM mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_MODEM; + + return 0; +} +#endif + +/** + * \brief Configure USART to work in SYNC mode and act as a master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_sync_master(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || usart_set_sync_master_baudrate(p_usart, + p_usart_opt->baudrate, ul_mck)) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Set normal mode and output clock as synchronous master. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL | US_MR_CLKO; + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in SYNC mode and act as a slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_sync_slave(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + usart_set_sync_slave_baudrate(p_usart); + + /* Check whether the input values are legal. */ + if (!p_usart_opt) { + return 1; + } + + /* Configure the USART option. */ + ul_reg_val |= p_usart_opt->char_length | p_usart_opt->parity_type | + p_usart_opt->channel_mode | p_usart_opt->stop_bits; + + /* Set normal mode. */ + ul_reg_val |= US_MR_USART_MODE_NORMAL; + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in RS485 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_rs485(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set RS485 mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_RS485; + + return 0; +} + +/** + * \brief Configure USART to work in IrDA mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_irda(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck) +{ + /* Initialize the USART as standard RS232. */ + if (usart_init_rs232(p_usart, p_usart_opt, ul_mck)) { + return 1; + } + + /* Set IrDA filter. */ + p_usart->US_IF = p_usart_opt->irda_filter; + + /* Set IrDA mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_IRDA; + + return 0; +} + +/** + * \brief Configure USART to work in ISO7816 mode. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_iso7816(Usart *p_usart, + const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + + /* Check whether the input values are legal. */ + if (!p_usart_opt || ((p_usart_opt->parity_type != US_MR_PAR_EVEN) && + (p_usart_opt->parity_type != US_MR_PAR_ODD))) { + return 1; + } + + if (p_usart_opt->protocol_type == ISO7816_T_0) { + ul_reg_val |= US_MR_USART_MODE_IS07816_T_0 | US_MR_NBSTOP_2_BIT | + (p_usart_opt->max_iterations << US_MR_MAX_ITERATION_Pos); + + if (p_usart_opt->bit_order) { + ul_reg_val |= US_MR_MSBF; + } + } else if (p_usart_opt->protocol_type == ISO7816_T_1) { + /* + * Only LSBF is used in the T=1 protocol, and max_iterations field + * is only used in T=0 mode. + */ + if (p_usart_opt->bit_order || p_usart_opt->max_iterations) { + return 1; + } + + /* Set USART mode to ISO7816, T=1, and always uses 1 stop bit. */ + ul_reg_val |= US_MR_USART_MODE_IS07816_T_1 | US_MR_NBSTOP_1_BIT; + } else { + return 1; + } + + /* Set up the baudrate. */ + if (usart_set_iso7816_clock(p_usart, p_usart_opt->iso7816_hz, ul_mck)) { + return 1; + } + + /* Set FIDI register: bit rate = iso7816_hz / fidi_ratio. */ + p_usart->US_FIDI = p_usart_opt->fidi_ratio; + + /* Set ISO7816 parity type in the MODE register. */ + ul_reg_val |= p_usart_opt->parity_type; + + if (p_usart_opt->inhibit_nack) { + ul_reg_val |= US_MR_INACK; + } + if (p_usart_opt->dis_suc_nack) { + ul_reg_val |= US_MR_DSNACK; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in SPI mode and act as a master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_spi_master(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + /* Check whether the input values are legal. */ + if (!p_usart_opt || (p_usart_opt->spi_mode > SPI_MODE_3) || + usart_set_spi_master_baudrate(p_usart, p_usart_opt->baudrate, + ul_mck)) { + return 1; + } + + /* Configure the character length bit in MR register. */ + ul_reg_val |= p_usart_opt->char_length; + + /* Set SPI master mode and channel mode. */ + ul_reg_val |= US_MR_USART_MODE_SPI_MASTER | US_MR_CLKO | + p_usart_opt->channel_mode; + + switch (p_usart_opt->spi_mode) { + case SPI_MODE_0: + ul_reg_val |= US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_1: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_2: + ul_reg_val |= US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + case SPI_MODE_3: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + default: + break; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +/** + * \brief Configure USART to work in SPI mode and act as a slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param p_usart_opt Pointer to sam_usart_opt_t instance. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_spi_slave(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt) +{ + static uint32_t ul_reg_val; + + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + ul_reg_val = 0; + usart_set_spi_slave_baudrate(p_usart); + + /* Check whether the input values are legal. */ + if (!p_usart_opt || p_usart_opt->spi_mode > SPI_MODE_3) { + return 1; + } + + /* Configure the character length bit in MR register. */ + ul_reg_val |= p_usart_opt->char_length; + + /* Set SPI slave mode and channel mode. */ + ul_reg_val |= US_MR_USART_MODE_SPI_SLAVE | p_usart_opt->channel_mode; + + switch (p_usart_opt->spi_mode) { + case SPI_MODE_0: + ul_reg_val |= US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_1: + ul_reg_val &= ~US_MR_CPHA; + ul_reg_val &= ~US_MR_CPOL; + break; + + case SPI_MODE_2: + ul_reg_val |= US_MR_CPHA; + ul_reg_val |= US_MR_CPOL; + break; + + case SPI_MODE_3: + ul_reg_val |= US_MR_CPOL; + ul_reg_val &= ~US_MR_CPHA; + break; + + default: + break; + } + + p_usart->US_MR |= ul_reg_val; + + return 0; +} + +#if (SAM3XA || SAM4L) + +/** + * \brief Configure USART to work in LIN mode and act as a LIN master. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lin_master(Usart *p_usart,uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + /* Set LIN master mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LIN_MASTER; + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + return 0; +} + +/** + * \brief Configure USART to work in LIN mode and act as a LIN slave. + * + * \note By default, the transmitter and receiver aren't enabled. + * + * \param p_usart Pointer to a USART instance. + * \param ul_baudrate Baudrate to be used. + * \param ul_mck USART module input clock frequency. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck) +{ + /* Reset the USART and shut down TX and RX. */ + usart_reset(p_usart); + + usart_enable_rx(p_usart); + usart_enable_tx(p_usart); + + /* Set LIN slave mode. */ + p_usart->US_MR = (p_usart->US_MR & ~US_MR_USART_MODE_Msk) | + US_MR_USART_MODE_LIN_SLAVE; + + /* Set up the baudrate. */ + if (usart_set_async_baudrate(p_usart, ul_baudrate, ul_mck)) { + return 1; + } + + return 0; +} + +/** + * \brief Abort the current LIN transmission. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_abort_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_LINABT; +} + +/** + * \brief Send a wakeup signal on the LIN bus. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_send_wakeup_signal(Usart *p_usart) +{ + p_usart->US_CR = US_CR_LINWKUP; +} + +/** + * \brief Configure the LIN node action, which should be one of PUBLISH, + * SUBSCRIBE or IGNORE. + * + * \param p_usart Pointer to a USART instance. + * \param uc_action 0 for PUBLISH, 1 for SUBSCRIBE, 2 for IGNORE. + */ +void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_NACT_Msk) | + (uc_action << US_LINMR_NACT_Pos); +} + +/** + * \brief Disable the parity check during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_parity(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_PARDIS; +} + +/** + * \brief Enable the parity check during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_parity(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_PARDIS; +} + +/** + * \brief Disable the checksum during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_checksum(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_CHKDIS; +} + +/** + * \brief Enable the checksum during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_checksum(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_CHKDIS; +} + +/** + * \brief Configure the checksum type during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type 0 for LIN 2.0 Enhanced checksum or 1 for LIN 1.3 Classic + * checksum. + */ +void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_CHKTYP) | + (uc_type << 4); +} + +/** + * \brief Configure the data length mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_mode Indicate the data length type: 0 if the data length is + * defined by the DLC of LIN mode register or 1 if the data length is defined + * by the bit 5 and 6 of the identifier. + */ +void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLM) | + (uc_mode << 5); +} + +/** + * \brief Disable the frame slot mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_frame_slot(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_FSDIS; +} + +/** + * \brief Enable the frame slot mode during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_frame_slot(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_FSDIS; +} + +/** + * \brief Configure the wakeup signal type during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_type Indicate the checksum type: 0 if the wakeup signal is a + * LIN 2.0 wakeup signal; 1 if the wakeup signal is a LIN 1.3 wakeup signal. + */ +void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_WKUPTYP) | + (uc_type << 7); +} + +/** + * \brief Configure the response data length if the data length is defined by + * the DLC field during the LIN communication. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len Indicate the response data length. + */ +void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_LINMR = (p_usart->US_LINMR & ~US_LINMR_DLC_Msk) | + ((uc_len - 1) << US_LINMR_DLC_Pos); +} + +/** + * \brief The LIN mode register is not written by the PDC. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_disable_pdc_mode(Usart *p_usart) +{ + p_usart->US_LINMR &= ~US_LINMR_PDCM; +} + +/** + * \brief The LIN mode register (except this flag) is written by the PDC. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_lin_enable_pdc_mode(Usart *p_usart) +{ + p_usart->US_LINMR |= US_LINMR_PDCM; +} + +/** + * \brief Configure the LIN identifier when USART works in LIN master mode. + * + * \param p_usart Pointer to a USART instance. + * \param uc_id The identifier to be transmitted. + */ +void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id) +{ + p_usart->US_LINIR = (p_usart->US_LINIR & ~US_LINIR_IDCHR_Msk) | + US_LINIR_IDCHR(uc_id); +} + +/** + * \brief Read the identifier when USART works in LIN mode. + * + * \param p_usart Pointer to a USART instance. + * + * \return The last identifier received in LIN slave mode or the last + * identifier transmitted in LIN master mode. + */ +uint8_t usart_lin_read_identifier(Usart *p_usart) +{ + return (p_usart->US_LINIR & US_LINIR_IDCHR_Msk); +} + +/** + * \brief Get data length. + * + * \param p_usart Pointer to a USART instance. + * + * \return Data length. + */ +uint8_t usart_lin_get_data_length(Usart *usart) +{ + if (usart->US_LINMR & US_LINMR_DLM) { + uint8_t data_length = 1 << ((usart->US_LINIR >> + (US_LINIR_IDCHR_Pos + 4)) & 0x03); + return data_length; + } else { + return ((usart->US_LINMR & US_LINMR_DLC_Msk) >> US_LINMR_DLC_Pos) + 1; + } +} + +#endif + +/** + * \brief Enable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_TXEN; +} + +/** + * \brief Disable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_tx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_TXDIS; +} + +/** + * \brief Immediately stop and disable USART transmitter. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_tx(Usart *p_usart) +{ + /* Reset transmitter */ + p_usart->US_CR = US_CR_RSTTX | US_CR_TXDIS; +} + +/** + * \brief Configure the transmit timeguard register. + * + * \param p_usart Pointer to a USART instance. + * \param timeguard The value of transmit timeguard. + */ +void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard) +{ + p_usart->US_TTGR = timeguard; +} + +/** + * \brief Enable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_rx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RXEN; +} + +/** + * \brief Disable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_rx(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RXDIS; +} + +/** + * \brief Immediately stop and disable USART receiver. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_rx(Usart *p_usart) +{ + /* Reset Receiver */ + p_usart->US_CR = US_CR_RSTRX | US_CR_RXDIS; +} + +/** + * \brief Configure the receive timeout register. + * + * \param p_usart Pointer to a USART instance. + * \param timeout The value of receive timeout. + */ +void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout) +{ + p_usart->US_RTOR = timeout; +} + +/** + * \brief Enable USART interrupts. + * + * \param p_usart Pointer to a USART peripheral. + * \param ul_sources Interrupt sources bit map. + */ +void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources) +{ + p_usart->US_IER = ul_sources; +} + +/** + * \brief Disable USART interrupts. + * + * \param p_usart Pointer to a USART peripheral. + * \param ul_sources Interrupt sources bit map. + */ +void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources) +{ + p_usart->US_IDR = ul_sources; +} + +/** + * \brief Read USART interrupt mask. + * + * \param p_usart Pointer to a USART peripheral. + * + * \return The interrupt mask value. + */ +uint32_t usart_get_interrupt_mask(Usart *p_usart) +{ + return p_usart->US_IMR; +} + +/** + * \brief Get current status. + * + * \param p_usart Pointer to a USART instance. + * + * \return The current USART status. + */ +uint32_t usart_get_status(Usart *p_usart) +{ + return p_usart->US_CSR; +} + +/** + * \brief Reset status bits (PARE, OVER, MANERR, UNRE and PXBRK in US_CSR). + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_status(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTSTA; +} + +/** + * \brief Start transmission of a break. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_start_tx_break(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STTBRK; +} + +/** + * \brief Stop transmission of a break. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_stop_tx_break(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STPBRK; +} + +/** + * \brief Start waiting for a character before clocking the timeout count. + * Reset the status bit TIMEOUT in US_CSR. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_start_rx_timeout(Usart *p_usart) +{ + p_usart->US_CR = US_CR_STTTO; +} + +/** + * \brief In Multidrop mode only, the next character written to the US_THR + * is sent with the address bit set. + * + * \param p_usart Pointer to a USART instance. + * \param ul_addr The address to be sent out. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr) +{ + if ((p_usart->US_MR & US_MR_PAR_MULTIDROP) != US_MR_PAR_MULTIDROP) { + return 1; + } + + p_usart->US_CR = US_CR_SENDA; + + if (usart_write(p_usart, ul_addr)) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Reset the ITERATION in US_CSR when the ISO7816 mode is enabled. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_iterations(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTIT; +} + +/** + * \brief Reset NACK in US_CSR. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_reset_nack(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RSTNACK; +} + +/** + * \brief Restart the receive timeout. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_restart_rx_timeout(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RETTO; +} + +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) + +/** + * \brief Drive the pin DTR to 0. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_DTR_pin_low(Usart *p_usart) +{ + p_usart->US_CR = US_CR_DTREN; +} + +/** + * \brief Drive the pin DTR to 1. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_DTR_pin_high(Usart *p_usart) +{ + p_usart->US_CR = US_CR_DTRDIS; +} + +#endif + +/** + * \brief Drive the pin RTS to 0. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_RTS_pin_low(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RTSEN; +} + +/** + * \brief Drive the pin RTS to 1. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_drive_RTS_pin_high(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RTSDIS; +} + +/** + * \brief Drive the slave select line NSS (RTS pin) to 0 in SPI master mode. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_spi_force_chip_select(Usart *p_usart) +{ + p_usart->US_CR = US_CR_FCS; +} + +/** + * \brief Drive the slave select line NSS (RTS pin) to 1 in SPI master mode. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_spi_release_chip_select(Usart *p_usart) +{ + p_usart->US_CR = US_CR_RCS; +} + +/** + * \brief Check if Transmit is Ready. + * Check if data have been loaded in USART_THR and are waiting to be loaded + * into the Transmit Shift Register (TSR). + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 No data is in the Transmit Holding Register. + * \retval 0 There is data in the Transmit Holding Register. + */ +uint32_t usart_is_tx_ready(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXRDY) > 0; +} + +/** + * \brief Check if Transmit Holding Register is empty. + * Check if the last data written in USART_THR have been loaded in TSR and the + * last data loaded in TSR have been transmitted. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmitter is empty. + * \retval 0 Transmitter is not empty. + */ +uint32_t usart_is_tx_empty(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXEMPTY) > 0; +} + +/** + * \brief Check if the received data are ready. + * Check if Data have been received and loaded into USART_RHR. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Some data has been received. + * \retval 0 No data has been received. + */ +uint32_t usart_is_rx_ready(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_RXRDY) > 0; +} + +/** + * \brief Check if one receive buffer is filled. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Receive is complete. + * \retval 0 Receive is still pending. + */ +uint32_t usart_is_rx_buf_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_ENDRX) > 0; +} + +/** + * \brief Check if one transmit buffer is empty. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmit is complete. + * \retval 0 Transmit is still pending. + */ +uint32_t usart_is_tx_buf_end(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_ENDTX) > 0; +} + +/** + * \brief Check if both receive buffers are full. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Receive buffers are full. + * \retval 0 Receive buffers are not full. + */ +uint32_t usart_is_rx_buf_full(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_RXBUFF) > 0; +} + +/** + * \brief Check if both transmit buffers are empty. + * + * \param p_usart Pointer to a USART instance. + * + * \retval 1 Transmit buffers are empty. + * \retval 0 Transmit buffers are not empty. + */ +uint32_t usart_is_tx_buf_empty(Usart *p_usart) +{ + return (p_usart->US_CSR & US_CSR_TXBUFE) > 0; +} + +/** + * \brief Write to USART Transmit Holding Register. + * + * \note Before writing user should check if tx is ready (or empty). + * + * \param p_usart Pointer to a USART instance. + * \param c Data to be sent. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_write(Usart *p_usart, uint32_t c) +{ + if (!(p_usart->US_CSR & US_CSR_TXRDY)) { + return 1; + } + + p_usart->US_THR = US_THR_TXCHR(c); + return 0; +} + +/** + * \brief Write to USART Transmit Holding Register. + * + * \note Before writing user should check if tx is ready (or empty). + * + * \param p_usart Pointer to a USART instance. + * \param c Data to be sent. + * + * \retval 0 on success. + * \retval 1 on failure. + */ +uint32_t usart_putchar(Usart *p_usart, uint32_t c) +{ + while (!(p_usart->US_CSR & US_CSR_TXRDY)) { + } + + p_usart->US_THR = US_THR_TXCHR(c); + + return 0; +} + +/** + * \brief Write one-line string through USART. + * + * \param p_usart Pointer to a USART instance. + * \param string Pointer to one-line string to be sent. + */ +void usart_write_line(Usart *p_usart, const char *string) +{ + while (*string != '\0') { + usart_putchar(p_usart, *string++); + } +} + +/** + * \brief Read from USART Receive Holding Register. + * + * \note Before reading user should check if rx is ready. + * + * \param p_usart Pointer to a USART instance. + * \param c Pointer where the one-byte received data will be stored. + * + * \retval 0 on success. + * \retval 1 if no data is available or errors. + */ +uint32_t usart_read(Usart *p_usart, uint32_t *c) +{ + if (!(p_usart->US_CSR & US_CSR_RXRDY)) { + return 1; + } + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + + return 0; +} + +/** + * \brief Read from USART Receive Holding Register. + * Before reading user should check if rx is ready. + * + * \param p_usart Pointer to a USART instance. + * \param c Pointer where the one-byte received data will be stored. + * + * \retval 0 Data has been received. + * \retval 1 on failure. + */ +uint32_t usart_getchar(Usart *p_usart, uint32_t *c) +{ + /* Wait until it's not empty or timeout has reached. */ + while (!(p_usart->US_CSR & US_CSR_RXRDY)) { + } + + /* Read character */ + *c = p_usart->US_RHR & US_RHR_RXCHR_Msk; + + return 0; +} + +#if (SAM3XA || SAM3U) +/** + * \brief Get Transmit address for DMA operation. + * + * \param p_usart Pointer to a USART instance. + * + * \return Transmit address for DMA access. + */ +uint32_t *usart_get_tx_access(Usart *p_usart) +{ + return (uint32_t *)&(p_usart->US_THR); +} + +/** + * \brief Get Receive address for DMA operation. + * + * \param p_usart Pointer to a USART instance. + * + * \return Receive address for DMA access. + */ +uint32_t *usart_get_rx_access(Usart *p_usart) +{ + return (uint32_t *)&(p_usart->US_RHR); +} +#endif + +#if (!SAM4L) +/** + * \brief Get USART PDC base address. + * + * \param p_usart Pointer to a UART instance. + * + * \return USART PDC registers base for PDC driver to access. + */ +Pdc *usart_get_pdc_base(Usart *p_usart) +{ + Pdc *p_pdc_base; + + p_pdc_base = (Pdc *)NULL; + + if (p_usart == USART0) { + p_pdc_base = PDC_USART0; + return p_pdc_base; + } +#ifdef PDC_USART1 + else if (p_usart == USART1) { + p_pdc_base = PDC_USART1; + return p_pdc_base; + } +#endif +#ifdef PDC_USART2 + else if (p_usart == USART2) { + p_pdc_base = PDC_USART2; + return p_pdc_base; + } +#endif +#ifdef PDC_USART3 + else if (p_usart == USART3) { + p_pdc_base = PDC_USART3; + return p_pdc_base; + } +#endif + + return p_pdc_base; +} +#endif + +/** + * \brief Enable write protect of USART registers. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_enable_writeprotect(Usart *p_usart) +{ + p_usart->US_WPMR = US_WPMR_WPEN | US_WPMR_WPKEY(US_WPKEY_VALUE); +} + +/** + * \brief Disable write protect of USART registers. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_disable_writeprotect(Usart *p_usart) +{ + p_usart->US_WPMR = US_WPMR_WPKEY(US_WPKEY_VALUE); +} + +/** + * \brief Get write protect status. + * + * \param p_usart Pointer to a USART instance. + * + * \return 0 if the peripheral is not protected. + * \return 16-bit Write Protect Violation Status otherwise. + */ +uint32_t usart_get_writeprotect_status(Usart *p_usart) +{ + uint32_t reg_value; + + reg_value = p_usart->US_WPSR; + if (reg_value & US_WPSR_WPVS) { + return (reg_value & US_WPSR_WPVSRC_Msk) >> US_WPSR_WPVSRC_Pos; + } else { + return 0; + } +} + +/** + * \brief Get the total number of errors that occur during an ISO7816 transfer. + * + * \param p_usart Pointer to a USART instance. + * + * \return The number of errors that occurred. + */ +uint8_t usart_get_error_number(Usart *p_usart) +{ + return (p_usart->US_NER & US_NER_NB_ERRORS_Msk); +} + +#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E) + +/** + * \brief Configure the transmitter preamble length when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len The transmitter preamble length, which should be 0 ~ 15. + */ +void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PL_Msk) | + US_MAN_TX_PL(uc_len); +} + +/** + * \brief Configure the transmitter preamble pattern when the Manchester + * encode/decode is enabled, which should be 0 ~ 3. + * + * \param p_usart Pointer to a USART instance. + * \param uc_pattern 0 if the preamble is composed of '1's; + * 1 if the preamble is composed of '0's; + * 2 if the preamble is composed of '01's; + * 3 if the preamble is composed of '10's. + */ +void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_PP_Msk) | + (uc_pattern << US_MAN_TX_PP_Pos); +} + +/** + * \brief Configure the transmitter Manchester polarity when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_polarity Indicate the transmitter Manchester polarity, which + * should be 0 or 1. + */ +void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_TX_MPOL) | + (uc_polarity << 12); +} + +/** + * \brief Configure the detected receiver preamble length when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_len The detected receiver preamble length, which should be 0 ~ 15. + */ +void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PL_Msk) | + US_MAN_RX_PL(uc_len); +} + +/** + * \brief Configure the detected receiver preamble pattern when the Manchester + * encode/decode is enabled, which should be 0 ~ 3. + * + * \param p_usart Pointer to a USART instance. + * \param uc_pattern 0 if the preamble is composed of '1's; + * 1 if the preamble is composed of '0's; + * 2 if the preamble is composed of '01's; + * 3 if the preamble is composed of '10's. + */ +void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_PP_Msk) | + (uc_pattern << US_MAN_RX_PP_Pos); +} + +/** + * \brief Configure the receiver Manchester polarity when the Manchester + * encode/decode is enabled. + * + * \param p_usart Pointer to a USART instance. + * \param uc_polarity Indicate the receiver Manchester polarity, which should + * be 0 or 1. + */ +void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity) +{ + p_usart->US_MAN = (p_usart->US_MAN & ~US_MAN_RX_MPOL) | + (uc_polarity << 28); +} + +/** + * \brief Enable drift compensation. + * + * \note The 16X clock mode must be enabled. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_man_enable_drift_compensation(Usart *p_usart) +{ + p_usart->US_MAN |= US_MAN_DRIFT; +} + +/** + * \brief Disable drift compensation. + * + * \param p_usart Pointer to a USART instance. + */ +void usart_man_disable_drift_compensation(Usart *p_usart) +{ + p_usart->US_MAN &= ~US_MAN_DRIFT; +} + +#endif + +#if SAM4L + +uint32_t usart_get_version(Usart *p_usart) +{ + return p_usart->US_VERSION; +} + +#endif + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/SAM3S4B/src/ASF/drivers1/usart/usart.h b/SAM3S4B/src/ASF/drivers1/usart/usart.h new file mode 100644 index 0000000..260fb6e --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/usart/usart.h @@ -0,0 +1,695 @@ +/** + * \file + * + * \brief Universal Synchronous Asynchronous Receiver Transmitter (USART) driver + * for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef USART_H_INCLUDED +#define USART_H_INCLUDED + +#include "compiler.h" + +/** + * \defgroup group_sam_drivers_usart Universal Synchronous Asynchronous Receiver + * Transmitter (USART). + * + * See \ref sam_usart_quickstart. + * + * This is a low-level driver implementation for the SAM Universal + * Synchronous/Asynchronous Receiver/Transmitter. + * + * @{ + */ + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** Clock phase. */ +#define SPI_CPHA (1 << 0) + +/** Clock polarity. */ +#define SPI_CPOL (1 << 1) + +/** SPI mode definition. */ +#define SPI_MODE_0 0 +#define SPI_MODE_1 (SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL) +#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA) + +/* Input parameters when initializing RS232 and similar modes. */ +typedef struct { + /* Set baud rate of the USART (unused in slave modes). */ + uint32_t baudrate; + + /* + * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, + * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or + * US_MR_MODE9. + */ + uint32_t char_length; + + /* + * Parity type, which should be one of the following: US_MR_PAR_EVEN, + * US_MR_PAR_ODD, US_MR_PAR_SPACE, US_MR_PAR_MARK, US_MR_PAR_NO + * or US_MR_PAR_MULTIDROP. + */ + uint32_t parity_type; + + /* + * Number of stop bits between two characters: US_MR_NBSTOP_1_BIT, + * US_MR_NBSTOP_1_5_BIT, US_MR_NBSTOP_2_BIT. + * \note US_MR_NBSTOP_1_5_BIT is supported in asynchronous modes only. + */ + uint32_t stop_bits; + + /* + * Run the channel in test mode, which should be one of following: + * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, + * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. + */ + uint32_t channel_mode; + + /* Filter of IrDA mode, useless in other modes. */ + uint32_t irda_filter; +} sam_usart_opt_t; + +/* Input parameters when initializing ISO7816 mode. */ +typedef struct { + /* Set the frequency of the ISO7816 clock. */ + uint32_t iso7816_hz; + + /* + * The number of ISO7816 clock ticks in every bit period (1 to 2047, + * 0 = disable clock). Baudrate rate = iso7816_hz / fidi_ratio. + */ + uint32_t fidi_ratio; + + /* + * How to calculate the parity bit: US_MR_PAR_EVEN for normal mode or + * US_MR_PAR_ODD for inverse mode. + */ + uint32_t parity_type; + + /* + * Inhibit Non Acknowledge: + * - 0: the NACK is generated; + * - 1: the NACK is not generated. + * + * \note This bit will be used only in ISO7816 mode, protocol T = 0 + * receiver. + */ + uint32_t inhibit_nack; + + /* + * Disable successive NACKs. + * - 0: NACK is sent on the ISO line as soon as a parity error occurs + * in the received character. Successive parity errors are counted up to + * the value in the max_iterations field. These parity errors generate + * a NACK on the ISO line. As soon as this value is reached, no additional + * NACK is sent on the ISO line. The ITERATION flag is asserted. + */ + uint32_t dis_suc_nack; + + /* Max number of repetitions (0 to 7). */ + uint32_t max_iterations; + + /* + * Bit order in transmitted characters: + * - 0: LSB first; + * - 1: MSB first. + */ + uint32_t bit_order; + + /* + * Which protocol is used: + * - 0: T = 0; + * - 1: T = 1. + */ + uint32_t protocol_type; +} usart_iso7816_opt_t; + +/* Input parameters when initializing SPI mode. */ +typedef struct { + /* Set the frequency of the SPI clock (unused in slave mode). */ + uint32_t baudrate; + + /* + * Number of bits, which should be one of the following: US_MR_CHRL_5_BIT, + * US_MR_CHRL_6_BIT, US_MR_CHRL_7_BIT, US_MR_CHRL_8_BIT or + * US_MR_MODE9. + */ + uint32_t char_length; + + /* + * Which SPI mode to use, which should be one of the following: + * SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3. + */ + uint32_t spi_mode; + + /* + * Run the channel in test mode, which should be one of following: + * US_MR_CHMODE_NORMAL, US_MR_CHMODE_AUTOMATIC, + * US_MR_CHMODE_LOCAL_LOOPBACK, US_MR_CHMODE_REMOTE_LOOPBACK. + */ + uint32_t channel_mode; +} usart_spi_opt_t; + +void usart_reset(Usart *p_usart); +uint32_t usart_init_rs232(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_hw_handshaking(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) +uint32_t usart_init_modem(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +#endif +uint32_t usart_init_sync_master(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_sync_slave(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt); +uint32_t usart_init_rs485(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_irda(Usart *p_usart, + const sam_usart_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_iso7816(Usart *p_usart, + const usart_iso7816_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_spi_master(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt, uint32_t ul_mck); +uint32_t usart_init_spi_slave(Usart *p_usart, + const usart_spi_opt_t *p_usart_opt); +#if (SAM3XA || SAM4L) +uint32_t usart_init_lin_master(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck); +uint32_t usart_init_lin_slave(Usart *p_usart, uint32_t ul_baudrate, + uint32_t ul_mck); +void usart_lin_abort_tx(Usart *p_usart); +void usart_lin_send_wakeup_signal(Usart *p_usart); +void usart_lin_set_node_action(Usart *p_usart, uint8_t uc_action); +void usart_lin_disable_parity(Usart *p_usart); +void usart_lin_enable_parity(Usart *p_usart); +void usart_lin_disable_checksum(Usart *p_usart); +void usart_lin_enable_checksum(Usart *p_usart); +void usart_lin_set_checksum_type(Usart *p_usart, uint8_t uc_type); +void usart_lin_set_data_len_mode(Usart *p_usart, uint8_t uc_mode); +void usart_lin_disable_frame_slot(Usart *p_usart); +void usart_lin_enable_frame_slot(Usart *p_usart); +void usart_lin_set_wakeup_signal_type(Usart *p_usart, uint8_t uc_type); +void usart_lin_set_response_data_len(Usart *p_usart, uint8_t uc_len); +void usart_lin_disable_pdc_mode(Usart *p_usart); +void usart_lin_enable_pdc_mode(Usart *p_usart); +void usart_lin_set_tx_identifier(Usart *p_usart, uint8_t uc_id); +uint8_t usart_lin_read_identifier(Usart *p_usart); +uint8_t usart_lin_get_data_length(Usart *usart); +#endif +void usart_enable_tx(Usart *p_usart); +void usart_disable_tx(Usart *p_usart); +void usart_reset_tx(Usart *p_usart); +void usart_set_tx_timeguard(Usart *p_usart, uint32_t timeguard); +void usart_enable_rx(Usart *p_usart); +void usart_disable_rx(Usart *p_usart); +void usart_reset_rx(Usart *p_usart); +void usart_set_rx_timeout(Usart *p_usart, uint32_t timeout); +void usart_enable_interrupt(Usart *p_usart, uint32_t ul_sources); +void usart_disable_interrupt(Usart *p_usart, uint32_t ul_sources); +uint32_t usart_get_interrupt_mask(Usart *p_usart); +uint32_t usart_get_status(Usart *p_usart); +void usart_reset_status(Usart *p_usart); +void usart_start_tx_break(Usart *p_usart); +void usart_stop_tx_break(Usart *p_usart); +void usart_start_rx_timeout(Usart *p_usart); +uint32_t usart_send_address(Usart *p_usart, uint32_t ul_addr); +void usart_reset_iterations(Usart *p_usart); +void usart_reset_nack(Usart *p_usart); +void usart_restart_rx_timeout(Usart *p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM4L || SAM4E) +void usart_drive_DTR_pin_low(Usart *p_usart); +void usart_drive_DTR_pin_high(Usart *p_usart); +#endif +void usart_drive_RTS_pin_low(Usart *p_usart); +void usart_drive_RTS_pin_high(Usart *p_usart); +void usart_spi_force_chip_select(Usart *p_usart); +void usart_spi_release_chip_select(Usart *p_usart); +uint32_t usart_is_tx_ready(Usart *p_usart); +uint32_t usart_is_tx_empty(Usart *p_usart); +uint32_t usart_is_rx_ready(Usart *p_usart); +uint32_t usart_is_rx_buf_end(Usart *p_usart); +uint32_t usart_is_tx_buf_end(Usart *p_usart); +uint32_t usart_is_rx_buf_full(Usart *p_usart); +uint32_t usart_is_tx_buf_empty(Usart *p_usart); +uint32_t usart_write(Usart *p_usart, uint32_t c); +uint32_t usart_putchar(Usart *p_usart, uint32_t c); +void usart_write_line(Usart *p_usart, const char *string); +uint32_t usart_read(Usart *p_usart, uint32_t *c); +uint32_t usart_getchar(Usart *p_usart, uint32_t *c); +#if (SAM3XA || SAM3U) +uint32_t *usart_get_tx_access(Usart *p_usart); +uint32_t *usart_get_rx_access(Usart *p_usart); +#endif +#if (!SAM4L) +Pdc *usart_get_pdc_base(Usart *p_usart); +#endif +void usart_enable_writeprotect(Usart *p_usart); +void usart_disable_writeprotect(Usart *p_usart); +uint32_t usart_get_writeprotect_status(Usart *p_usart); +uint8_t usart_get_error_number(Usart *p_usart); +#if (SAM3S || SAM4S || SAM3U || SAM3XA || SAM4L || SAM4E) +void usart_man_set_tx_pre_len(Usart *p_usart, uint8_t uc_len); +void usart_man_set_tx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); +void usart_man_set_tx_polarity(Usart *p_usart, uint8_t uc_polarity); +void usart_man_set_rx_pre_len(Usart *p_usart, uint8_t uc_len); +void usart_man_set_rx_pre_pattern(Usart *p_usart, uint8_t uc_pattern); +void usart_man_set_rx_polarity(Usart *p_usart, uint8_t uc_polarity); +void usart_man_enable_drift_compensation(Usart *p_usart); +void usart_man_disable_drift_compensation(Usart *p_usart); +#endif + +#if SAM4L +uint32_t usart_get_version(Usart *p_usart); +#endif + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +//! @} + +/** + * \page sam_usart_quickstart Quick start guide for the SAM USART module + * + * This is the quick start guide for the \ref group_sam_drivers_usart + * "USART module", with step-by-step instructions on how to configure and + * use the driver in a selection of use cases. + * + * The use cases contain several code fragments. The code fragments in the + * steps for setup can be copied into a custom initialization function, while + * the steps for usage can be copied into, e.g., the main application function. + * + * \note Some SAM devices contain both USART and UART modules, with the latter + * being a subset in functionality of the former but physically separate + * peripherals. UART modules are compatible with the USART driver, but + * only for the functions and modes supported by the base UART driver. + * + * \section usart_basic_use_case Basic use case + * \section usart_use_cases USART use cases + * - \ref usart_basic_use_case + * - \subpage usart_use_case_1 + * - \subpage usart_use_case_2 + * + * \section usart_basic_use_case Basic use case - transmit a character + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * \section usart_basic_use_case_setup Setup steps + * + * \subsection usart_basic_use_case_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref ioport_group "Common IOPORT API (ioport)" + * + * \subsection usart_basic_use_case_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.) + * \code + * #define USART_SERIAL USART0 + * #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + * #define USART_SERIAL_PIO PINS_USART_PIO + * #define USART_SERIAL_TYPE PINS_USART_TYPE + * #define USART_SERIAL_PINS PINS_USART_PINS + * #define USART_SERIAL_MASK PINS_USART_MASK + * #define USART_SERIAL_BAUDRATE 9600 + * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + * #define USART_SERIAL_PARITY US_MR_PAR_NO + * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT + * \endcode + * + * Add to application initialization: + * \code + * sysclk_init(); + * + * board_init(); + * + * const sam_usart_opt_t usart_console_settings = { + * USART_SERIAL_BAUDRATE, + * USART_SERIAL_CHAR_LENGTH, + * USART_SERIAL_PARITY, + * USART_SERIAL_STOP_BIT, + * US_MR_CHMODE_NORMAL + * }; + * + * sysclk_enable_peripheral_clock(USART_SERIAL_ID); + * + * usart_init_rs232(USART_SERIAL, &usart_console_settings, + * sysclk_get_main_hz()); + * usart_enable_tx(USART_SERIAL); + * usart_enable_rx(USART_SERIAL); + * \endcode + * + * \subsection usart_basic_use_case_setup_flow Workflow + * -# Initialize system clock: + * \code + * sysclk_init(); + * \endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + * board_init(); + * \endcode + * \note Set the define in conf_board.h file. + * -# Create USART options struct: + * \code + * const sam_usart_opt_t usart_console_settings = { + * USART_SERIAL_BAUDRATE, + * USART_SERIAL_CHAR_LENGTH, + * USART_SERIAL_PARITY, + * USART_SERIAL_STOP_BIT, + * US_MR_CHMODE_NORMAL + * }; + * \endcode + * -# Enable the clock to the USART module: + * \code + * sysclk_enable_peripheral_clock(USART_SERIAL_ID); + * \endcode + * -# Initialize the USART module in RS232 mode: + * \code + * usart_init_rs232(USART_SERIAL, &usart_console_settings, + * sysclk_get_main_hz()); + * \endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + * usart_enable_tx(USART_SERIAL); + * usart_enable_rx(USART_SERIAL); + * \endcode + * + * \section usart_basic_use_case_usage Usage steps + * + * \subsection usart_basic_use_case_usage_code Example code + * Add to application C-file: + * \code + * usart_putchar(USART_SERIAL, 'a'); + * \endcode + * + * \subsection usart_basic_use_case_usage_flow Workflow + * -# Send an 'a' character via USART + * \code usart_putchar(USART_SERIAL, 'a'); \endcode + */ + +/** + * \page usart_use_case_1 USART receive character and echo back + * + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. + * + * \section usart_use_case_1_setup Setup steps + * + * \subsection usart_use_case_1_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref ioport_group "Common IOPORT API (ioport)" + * + * \subsection usart_use_case_1_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.): + * \code + * #define USART_SERIAL USART0 + * #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + * #define USART_SERIAL_PIO PINS_USART_PIO + * #define USART_SERIAL_TYPE PINS_USART_TYPE + * #define USART_SERIAL_PINS PINS_USART_PINS + * #define USART_SERIAL_MASK PINS_USART_MASK + * #define USART_SERIAL_BAUDRATE 9600 + * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + * #define USART_SERIAL_PARITY US_MR_PAR_NO + * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT + * \endcode + * + * A variable for the received byte must be added: + * \code + * uint32_t received_byte; + * \endcode + * + * Add to application initialization: + * \code + * sysclk_init(); + * + * board_init(); + * + * const sam_usart_opt_t usart_console_settings = { + * USART_SERIAL_BAUDRATE, + * USART_SERIAL_CHAR_LENGTH, + * USART_SERIAL_PARITY, + * USART_SERIAL_STOP_BIT, + * US_MR_CHMODE_NORMAL + * }; + * + * sysclk_enable_peripheral_clock(USART_SERIAL_ID); + * + * usart_init_rs232(USART_SERIAL, &usart_console_settings, + * sysclk_get_main_hz()); + * usart_enable_tx(USART_SERIAL); + * usart_enable_rx(USART_SERIAL); + * \endcode + * + * \subsection usart_use_case_1_setup_flow Workflow + * -# Initialize system clock: + * \code + * sysclk_init(); + * \endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + * board_init(); + * \endcode + * \note Set the define in conf_board.h file. + * -# Create USART options struct: + * \code + * const sam_usart_opt_t usart_console_settings = { + * USART_SERIAL_BAUDRATE, + * USART_SERIAL_CHAR_LENGTH, + * USART_SERIAL_PARITY, + * USART_SERIAL_STOP_BIT, + * US_MR_CHMODE_NORMAL + * }; + * \endcode + * -# Enable the clock to the USART module: + * \code sysclk_enable_peripheral_clock(USART_SERIAL_ID); \endcode + * -# Initialize the USART module in RS232 mode: + * \code + * usart_init_rs232(USART_SERIAL, &usart_console_settings, + * sysclk_get_main_hz()); + * \endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + * usart_enable_tx(USART_SERIAL); + * usart_enable_rx(USART_SERIAL); + * \endcode + * + * \section usart_use_case_1_usage Usage steps + * + * \subsection usart_use_case_1_usage_code Example code + * Add to, e.g., main loop in application C-file: + * \code + * received_byte = usart_getchar(USART_SERIAL); + * usart_putchar(USART_SERIAL, received_byte); + * \endcode + * + * \subsection usart_use_case_1_usage_flow Workflow + * -# Wait for reception of a character: + * \code usart_getchar(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * \code usart_putchar(USART_SERIAL, received_byte); \endcode + */ + +/** + * \page usart_use_case_2 USART receive character and echo back via interrupts + * + * In this use case, the USART module is configured for: + * - Using USART0 + * - Baudrate: 9600 + * - Character length: 8 bit + * - Parity mode: Disabled + * - Stop bit: None + * - RS232 mode + * + * The use case waits for a received character on the configured USART and + * echoes the character back to the same USART. The character reception is + * performed via an interrupt handler, rather than the polling method used + * in \ref usart_use_case_1. + * + * \section usart_use_case_2_setup Setup steps + * + * \subsection usart_use_case_2_setup_prereq Prerequisites + * -# \ref sysclk_group "System Clock Management (sysclock)" + * -# \ref pio_group "Parallel Input/Output Controller (pio)" + * -# \ref pmc_group "Power Management Controller (pmc)" + * + * \subsection usart_use_case_2_setup_code Example code + * The following configuration must be added to the project (typically to a + * conf_usart.h file, but it can also be added to your main application file.): + * \code + * #define USART_SERIAL USART0 + * #define USART_SERIAL_ID ID_USART0 //USART0 for sam4l + * #define USART_SERIAL_ISR_HANDLER USART0_Handler + * #define USART_SERIAL_PIO PINS_USART_PIO + * #define USART_SERIAL_TYPE PINS_USART_TYPE + * #define USART_SERIAL_PINS PINS_USART_PINS + * #define USART_SERIAL_MASK PINS_USART_MASK + * #define USART_SERIAL_BAUDRATE 9600 + * #define USART_SERIAL_CHAR_LENGTH US_MR_CHRL_8_BIT + * #define USART_SERIAL_PARITY US_MR_PAR_NO + * #define USART_SERIAL_STOP_BIT US_MR_NBSTOP_1_BIT + * \endcode + * + * A variable for the received byte must be added: + * \code + * uint32_t received_byte; + * \endcode + * + * Add to application initialization: + * \code + * sysclk_init(); + * + * board_init(); + * + * const sam_usart_opt_t usart_console_settings = { + * USART_SERIAL_BAUDRATE, + * USART_SERIAL_CHAR_LENGTH, + * USART_SERIAL_PARITY, + * USART_SERIAL_STOP_BIT, + * US_MR_CHMODE_NORMAL + * }; + * + * sysclk_enable_peripheral_clock(USART_SERIAL_ID); + * + * usart_init_rs232(USART_SERIAL, &usart_console_settings, + * sysclk_get_main_hz()); + * usart_enable_tx(USART_SERIAL); + * usart_enable_rx(USART_SERIAL); + * + * usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); + * NVIC_EnableIRQ(USART_SERIAL_IRQ); + * \endcode + * + * \subsection usart_use_case_2_setup_flow Workflow + * -# Initialize system clock: + * \code + * sysclk_init(); + * \endcode + * -# Configure the USART Tx and Rx pins by call the board init function: + * \code + * board_init(); + * \endcode + * \note Set the define in conf_board.h file. + * -# Create USART options struct: + * \code + * const sam_usart_opt_t usart_console_settings = { + * USART_SERIAL_BAUDRATE, + * USART_SERIAL_CHAR_LENGTH, + * USART_SERIAL_PARITY, + * USART_SERIAL_STOP_BIT, + * US_MR_CHMODE_NORMAL + * }; + * \endcode + * -# Enable the clock to the USART module: + * \code sysclk_enable_peripheral_clock(USART_SERIAL_ID); \endcode + * -# Initialize the USART module in RS232 mode: + * \code + * usart_init_rs232(USART_SERIAL, &usart_console_settings, + * sysclk_get_main_hz()); + * \endcode + * -# Enable the Rx and Tx modes of the USART module: + * \code + * usart_enable_tx(USART_SERIAL); + * usart_enable_rx(USART_SERIAL); + * \endcode + * -# Enable the USART character reception interrupt, and general interrupts + * for the USART module. + * \code + * usart_enable_interrupt(USART_SERIAL, US_IER_RXRDY); + * NVIC_EnableIRQ(USART_SERIAL_IRQ); + * \endcode + * \section usart_use_case_2_usage Usage steps + * + * \subsection usart_use_case_2_usage_code Example code + * Add to your main application C-file the USART interrupt handler: + * \code + * void USART_SERIAL_ISR_HANDLER(void) + * { + * uint32_t dw_status = usart_get_status(USART_SERIAL); + * + * if (dw_status & US_CSR_RXRDY) { + * uint32_t received_byte; + * + * usart_read(USART_SERIAL, &received_byte); + * usart_write(USART_SERIAL, received_byte); + * } + * } + * \endcode + * + * \subsection usart_use_case_2_usage_flow Workflow + * -# When the USART ISR fires, retrieve the USART module interrupt flags: + * \code uint32_t dw_status = usart_get_status(USART_SERIAL); \endcode + * -# Check if the USART Receive Character interrupt has fired: + * \code if (dw_status & US_CSR_RXRDY) \endcode + * -# If a character has been received, fetch it into a temporary variable: + * \code usart_read(USART_SERIAL, &received_byte); \endcode + * -# Echo the character back: + * \code usart_write(USART_SERIAL, received_byte); \endcode + */ + +#endif /* USART_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/drivers1/usart/usart_serial_example/sam3s4c_sam3s_ek/conf_example.h b/SAM3S4B/src/ASF/drivers1/usart/usart_serial_example/sam3s4c_sam3s_ek/conf_example.h new file mode 100644 index 0000000..3f3dd89 --- /dev/null +++ b/SAM3S4B/src/ASF/drivers1/usart/usart_serial_example/sam3s4c_sam3s_ek/conf_example.h @@ -0,0 +1,60 @@ +/** + * \file + * + * \brief USART serial example configuration. + * + * Copyright (c) 2011 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef CONF_EXAMPLE_H_INCLUDED +#define CONF_EXAMPLE_H_INCLUDED + +#include "conf_board.h" +#include "conf_clock.h" + +#define BOARD_ID_USART ID_USART0 + +#define BOARD_USART USART0 + +#define BOARD_USART_BAUDRATE 9600 + +#define USART_Handler USART0_Handler + +#define USART_IRQn USART0_IRQn + +#endif /* CONF_EXAMPLE_H_INCLUDED */ diff --git a/SAM3S4B/src/ASF/efc.c b/SAM3S4B/src/ASF/efc.c new file mode 100644 index 0000000..ef8986f --- /dev/null +++ b/SAM3S4B/src/ASF/efc.c @@ -0,0 +1,400 @@ +/** + * \file + * + * \brief Enhanced Embedded Flash Controller (EEFC) driver for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "efc.h" +#include + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/** + * \defgroup sam_drivers_efc_group Enhanced Embedded Flash Controller (EEFC) + * + * The Enhanced Embedded Flash Controller ensures the interface of the Flash + * block with the 32-bit internal bus. + * + * @{ + */ + +/* Address definition for read operation */ +#if (SAM3XA || SAM3U4 || SAM4SD16 || SAM4SD32) +# define READ_BUFF_ADDR0 IFLASH0_ADDR +# define READ_BUFF_ADDR1 IFLASH1_ADDR +#elif (SAM3S || SAM3N || SAM4E || SAM4N) +# define READ_BUFF_ADDR IFLASH_ADDR +#elif (SAM3U || SAM4S) +# define READ_BUFF_ADDR IFLASH0_ADDR +#else +# warning Only reading unique ID for sam3/4 is implemented. +#endif + +/* Flash Writing Protection Key */ +#define FWP_KEY 0x5Au + +#if (SAM4S || SAM4E || SAM4N) +#define EEFC_FCR_FCMD(value) \ + ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR) +#else +#define EEFC_ERROR_FLAGS (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE) +#endif + +//uint32_t ul_rc; + +/* + * Local function declaration. + * Because they are RAM functions, they need 'extern' declaration. + */ +extern void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr); +extern uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr); + +/** + * \brief Initialize the EFC controller. + * + * \param ul_access_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. + * \param ul_fws The number of wait states in cycle (no shift). + * + * \return 0 if successful. + */ +uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws) +{ + efc_write_fmr(p_efc, ul_access_mode | EEFC_FMR_FWS(ul_fws)); + return EFC_RC_OK; +} + +/** + * \brief Enable the flash ready interrupt. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_enable_frdy_interrupt(Efc *p_efc) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR; + + efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FRDY); +} + +/** + * \brief Disable the flash ready interrupt. + * + * \param p_efc Pointer to an EFC instance. + */ +void efc_disable_frdy_interrupt(Efc *p_efc) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR; + + efc_write_fmr(p_efc, ul_fmr & (~EEFC_FMR_FRDY)); +} + +/** + * \brief Set flash access mode. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_mode 0 for 128-bit, EEFC_FMR_FAM for 64-bit. + */ +void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FAM); + + efc_write_fmr(p_efc, ul_fmr | ul_mode); +} + +/** + * \brief Get flash access mode. + * + * \param p_efc Pointer to an EFC instance. + * + * \return 0 for 128-bit or EEFC_FMR_FAM for 64-bit. + */ +uint32_t efc_get_flash_access_mode(Efc *p_efc) +{ + return (p_efc->EEFC_FMR & EEFC_FMR_FAM); +} + +/** + * \brief Set flash wait state. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_fws The number of wait states in cycle (no shift). + */ +void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws) +{ + uint32_t ul_fmr = p_efc->EEFC_FMR & (~EEFC_FMR_FWS_Msk); + + efc_write_fmr(p_efc, ul_fmr | EEFC_FMR_FWS(ul_fws)); +} + +/** + * \brief Get flash wait state. + * + * \param p_efc Pointer to an EFC instance. + * + * \return The number of wait states in cycle (no shift). + */ +uint32_t efc_get_wait_state(Efc *p_efc) +{ + return ((p_efc->EEFC_FMR & EEFC_FMR_FWS_Msk) >> EEFC_FMR_FWS_Pos); +} + +/** + * \brief Perform the given command and wait until its completion (or an error). + * + * \note Unique ID commands are not supported, use efc_read_unique_id. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_command Command to perform. + * \param ul_argument Optional command argument. + * + * \note This function will automatically choose to use IAP function. + * + * \return 0 if successful, otherwise returns an error code. + */ +uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command, + uint32_t ul_argument) +{ + //unsigned int status; + + /* Unique ID commands are not supported. */ + if (ul_command == EFC_FCMD_STUI || ul_command == EFC_FCMD_SPUI) { + return EFC_RC_NOT_SUPPORT; + } + +#if (SAM3XA || SAM3U4) + /* Use IAP function with 2 parameters in ROM. */ + static uint32_t(*iap_perform_command) (uint32_t, uint32_t); + uint32_t ul_efc_nb = (p_efc == EFC0) ? 0 : 1; + + iap_perform_command = + (uint32_t(*)(uint32_t, uint32_t)) + *((uint32_t *) CHIP_FLASH_IAP_ADDRESS); + iap_perform_command(ul_efc_nb, + EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); + return (p_efc->EEFC_FSR & EEFC_ERROR_FLAGS); + +#elif (SAM3N || SAM3S || SAM4S || SAM3U || SAM4E || SAM4N) + /* Use IAP function with 2 parameter in ROM. */ + static uint32_t(*iap_perform_command) (uint32_t, uint32_t); + + iap_perform_command = + (uint32_t(*)(uint32_t, uint32_t)) + *((uint32_t *) CHIP_FLASH_IAP_ADDRESS); + + +#if SAM4S + uint32_t ul_efc_nb = (p_efc == EFC0) ? 0 : 1; + iap_perform_command(ul_efc_nb, + EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); +#elif SAM4E || SAM4N + iap_perform_command(0, + EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); +#else + iap_perform_command(0, + EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); +#endif + return (p_efc->EEFC_FSR & EEFC_ERROR_FLAGS); +#else + /* Use RAM Function. */ + return iap_perform_command(0, + EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(ul_argument) | + EEFC_FCR_FCMD(ul_command)); + +#endif +} + +/** + * \brief Get the current status of the EEFC. + * + * \note This function clears the value of some status bits (FLOCKE, FCMDE). + * + * \param p_efc Pointer to an EFC instance. + * + * \return The current status. + */ +uint32_t efc_get_status(Efc *p_efc) +{ + return p_efc->EEFC_FSR; +} + +/** + * \brief Get the result of the last executed command. + * + * \param p_efc Pointer to an EFC instance. + * + * \return The result of the last executed command. + */ +uint32_t efc_get_result(Efc *p_efc) +{ + return p_efc->EEFC_FRR; +} + +/** + * \brief Perform read sequence. Supported sequences are read Unique ID and + * read User Signature + * + * \param p_efc Pointer to an EFC instance. + * \param ul_cmd_st Start command to perform. + * \param ul_cmd_sp Stop command to perform. + * \param p_ul_buf Pointer to an data buffer. + * \param ul_size Buffer size. + * + * \return 0 if successful, otherwise returns an error code. + */ +RAMFUNC +uint32_t efc_perform_read_sequence(Efc *p_efc, + uint32_t ul_cmd_st, uint32_t ul_cmd_sp, + uint32_t *p_ul_buf, uint32_t ul_size) +{ + volatile uint32_t ul_status; + uint32_t ul_cnt; + +#if (SAM3U4 || SAM3XA || SAM4SD16 || SAM4SD32) + uint32_t *p_ul_data = + (uint32_t *) ((p_efc == EFC0) ? + READ_BUFF_ADDR0 : READ_BUFF_ADDR1); +#elif (SAM3S || SAM4S || SAM3N || SAM3U || SAM4E || SAM4N) + uint32_t *p_ul_data = (uint32_t *) READ_BUFF_ADDR; +#else + return EFC_RC_NOT_SUPPORT; +#endif + + if (p_ul_buf == NULL) { + return EFC_RC_INVALID; + } + + p_efc->EEFC_FMR |= (0x1u << 16); + + /* Send the Start Read command */ +#if (SAM4S || SAM4E || SAM4N) + p_efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) + | EEFC_FCR_FCMD(ul_cmd_st); +#else + p_efc->EEFC_FCR = EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) + | EEFC_FCR_FCMD(ul_cmd_st); +#endif + /* Wait for the FRDY bit in the Flash Programming Status Register + * (EEFC_FSR) falls. + */ + do { + ul_status = p_efc->EEFC_FSR; + } while ((ul_status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY); + + /* The data is located in the first address of the Flash + * memory mapping. + */ + for (ul_cnt = 0; ul_cnt < ul_size; ul_cnt++) { + p_ul_buf[ul_cnt] = p_ul_data[ul_cnt]; + } + + /* To stop the read mode */ + p_efc->EEFC_FCR = +#if (SAM4S || SAM4E || SAM4N) + EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(0) | + EEFC_FCR_FCMD(ul_cmd_sp); +#else + EEFC_FCR_FKEY(FWP_KEY) | EEFC_FCR_FARG(0) | + EEFC_FCR_FCMD(ul_cmd_sp); +#endif + /* Wait for the FRDY bit in the Flash Programming Status Register (EEFC_FSR) + * rises. + */ + do { + ul_status = p_efc->EEFC_FSR; + } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); + + p_efc->EEFC_FMR &= ~(0x1u << 16); + + return EFC_RC_OK; +} + +/** + * \brief Set mode register. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_fmr Value of mode register + */ +RAMFUNC +void efc_write_fmr(Efc *p_efc, uint32_t ul_fmr) +{ + p_efc->EEFC_FMR = ul_fmr; +} + +/** + * \brief Perform command. + * + * \param p_efc Pointer to an EFC instance. + * \param ul_fcr Flash command. + * + * \return The current status. + */ +RAMFUNC +uint32_t efc_perform_fcr(Efc *p_efc, uint32_t ul_fcr) +{ + volatile uint32_t ul_status; + + p_efc->EEFC_FCR = ul_fcr; + + do { + ul_status = p_efc->EEFC_FSR; + } while ((ul_status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); + + return (ul_status & EEFC_ERROR_FLAGS); +} + +//@} + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond diff --git a/SAM3S4B/src/ASF/efc.h b/SAM3S4B/src/ASF/efc.h new file mode 100644 index 0000000..f4105d0 --- /dev/null +++ b/SAM3S4B/src/ASF/efc.h @@ -0,0 +1,135 @@ +/** + * \file + * + * \brief Embedded Flash Controller (EFC) driver for SAM. + * + * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef EFC_H_INCLUDED +#define EFC_H_INCLUDED + +#include "compiler.h" + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/// @endcond + +/*! \name EFC return codes */ +//! @{ +typedef enum efc_rc { + EFC_RC_OK = 0, //!< Operation OK + EFC_RC_YES = 0, //!< Yes + EFC_RC_NO = 1, //!< No + EFC_RC_ERROR = 1, //!< General error + EFC_RC_INVALID, //!< Invalid argument input + EFC_RC_NOT_SUPPORT = 0xFFFFFFFF //!< Operation is not supported +} efc_rc_t; +//! @} + +/*! \name EFC command */ +//! @{ +#define EFC_FCMD_GETD 0x00 //!< Get Flash Descriptor +#define EFC_FCMD_WP 0x01 //!< Write page +#define EFC_FCMD_WPL 0x02 //!< Write page and lock +#define EFC_FCMD_EWP 0x03 //!< Erase page and write page +#define EFC_FCMD_EWPL 0x04 //!< Erase page and write page then lock +#define EFC_FCMD_EA 0x05 //!< Erase all +#if (SAM3SD8) +#define EFC_FCMD_EPL 0x06 //!< Erase plane +#endif +#if (SAM4S || SAM4E || SAM4N) +#define EFC_FCMD_EPA 0x07 //!< Erase pages +#endif +#define EFC_FCMD_SLB 0x08 //!< Set Lock Bit +#define EFC_FCMD_CLB 0x09 //!< Clear Lock Bit +#define EFC_FCMD_GLB 0x0A //!< Get Lock Bit +#define EFC_FCMD_SGPB 0x0B //!< Set GPNVM Bit +#define EFC_FCMD_CGPB 0x0C //!< Clear GPNVM Bit +#define EFC_FCMD_GGPB 0x0D //!< Get GPNVM Bit +#define EFC_FCMD_STUI 0x0E //!< Start unique ID +#define EFC_FCMD_SPUI 0x0F //!< Stop unique ID +#if (!SAM3U && !SAM3SD8 && !SAM3S8) +#define EFC_FCMD_GCALB 0x10 //!< Get CALIB Bit +#endif +#if (SAM4S || SAM4E || SAM4N) +#define EFC_FCMD_ES 0x11 //!< Erase sector +#define EFC_FCMD_WUS 0x12 //!< Write user signature +#define EFC_FCMD_EUS 0x13 //!< Erase user signature +#define EFC_FCMD_STUS 0x14 //!< Start read user signature +#define EFC_FCMD_SPUS 0x15 //!< Stop read user signature +#endif +//! @} + +/*! The IAP function entry address */ +#define CHIP_FLASH_IAP_ADDRESS (IROM_ADDR + 8) + +/*! \name EFC access mode */ +//! @{ +#define EFC_ACCESS_MODE_128 0 +#define EFC_ACCESS_MODE_64 EEFC_FMR_FAM +//! @} + +uint32_t efc_init(Efc *p_efc, uint32_t ul_access_mode, uint32_t ul_fws); +void efc_enable_frdy_interrupt(Efc *p_efc); +void efc_disable_frdy_interrupt(Efc *p_efc); +void efc_set_flash_access_mode(Efc *p_efc, uint32_t ul_mode); +uint32_t efc_get_flash_access_mode(Efc *p_efc); +void efc_set_wait_state(Efc *p_efc, uint32_t ul_fws); +uint32_t efc_get_wait_state(Efc *p_efc); +uint32_t efc_perform_command(Efc *p_efc, uint32_t ul_command, + uint32_t ul_argument); +uint32_t efc_get_status(Efc *p_efc); +uint32_t efc_get_result(Efc *p_efc); +uint32_t efc_perform_read_sequence(Efc *p_efc, + uint32_t ul_cmd_st, uint32_t ul_cmd_sp, + uint32_t *p_ul_buf, uint32_t ul_size); + +/// @cond 0 +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/// @endcond + +#endif /* EFC_H_INCLUDED */