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CHJ/user/Protocol/UserModbusMemAdr.h

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2026-03-20 21:19:53 +08:00
#ifndef __UserModbusMemAdr_h__
#define __UserModbusMemAdr_h__
//******************************************************************************
//#define MEM_ADDR_REG_0X30
#define PROTOCOL MEM_ADDR_REG_0X80 // MEM_ADDR_REG_0X80 Э<><D0AD>
#define SLAVER_ADDR MEM_ADDR_REG_0X81 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define COM_BPS MEM_ADDR_REG_0X82 // <20><><EFBFBD><EFBFBD><EFBFBD>ʣ<EFBFBD>0-4800<30><30>1-9600<30><30>2-19200<30><30>3-38400<30><30>4-57600<30><30>5-115200<30><30>
#define OUT_MIN_FLOW MEM_ADDR_REG_0X83 // <20><>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>3λС<CEBB><D0A1><EFBFBD><EFBFBD>
#define OUT_MIN_FLOW_L MEM_ADDR_REG_0X84
#define OUT_MAX_FLOW MEM_ADDR_REG_0X85 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>3λС<CEBB><D0A1><EFBFBD><EFBFBD>
#define OUT_MAX_FLOW_L MEM_ADDR_REG_0X86
#define OUT_ANALOG_MIN MEM_ADDR_REG_0X87 // <20><>Сģ<D0A1><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>mv<6D><76>
#define OUT_ANALOG_MIN_L MEM_ADDR_REG_0X88
#define OUT_ANALOG_MAX MEM_ADDR_REG_0X89 // <20><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>mv<6D><76>
#define OUT_ANALOG_MAX_L MEM_ADDR_REG_0X8A
#define GCF_B MEM_ADDR_REG_0X8B // GCF* (<28><><EFBFBD>Ȳ<EFBFBD><C8B2><EFBFBD>PASSWORD 0XAA55)
#define FILTER_DEPTH MEM_ADDR_REG_0X8C // <20>˲<EFBFBD><CBB2><EFBFBD><EFBFBD><EFBFBD>
#define RESPONSE_TIME MEM_ADDR_REG_0X8D // <20><>Ӧʱ<D3A6><CAB1>*
#define GAS_OFFSET MEM_ADDR_REG_0X8E // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>㣨C TYPE<50><45>
#define GAS_OFFSET_A MEM_ADDR_REG_0X8F // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>㣨A TYPE<50><45>
#define FLOW_UNIT MEM_ADDR_REG_0X90 // <20><>λ
#define AIR_FACTOR MEM_ADDR_REG_0X91 // <20><><EFBFBD><EFBFBD>ʶ<EFBFBD><CAB6>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD>ֵ
#define FACTOR_VTH MEM_ADDR_REG_0X92 // ʶ<><CAB6><EFBFBD>Ƚ<EFBFBD><C8BD><EFBFBD><EFBFBD><EFBFBD>
#define PULSE_UNIT MEM_ADDR_REG_0X93 //
#define PULSE_LEVEL MEM_ADDR_REG_0X94 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽ<EFBFBD><C6BD><EFBFBD><EFBFBD>
#define SAMPLE_PERIOD MEM_ADDR_REG_0X95 //
#define ALARM_ACC MEM_ADDR_REG_0X96 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define ALARM_ACC_L MEM_ADDR_REG_0X97
#define ALARM_UPPER_FLOW MEM_ADDR_REG_0X98 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define ALARM_UPPER_FLOW_L MEM_ADDR_REG_0X99
#define ALARM_LOWER_FLOW MEM_ADDR_REG_0X9A // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define ALARM_LOWER_FLOW_L MEM_ADDR_REG_0X9B
#define ALARM_FUN MEM_ADDR_REG_0X9C // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define ALARM_OUT_DELAY MEM_ADDR_REG_0X9D // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ (<28><>λ<EFBFBD><CEBB>s)
#define COM_DECIMAL MEM_ADDR_REG_0X9E
#define RECORD_TIME MEM_ADDR_REG_0X9F // <20><>¼<EFBFBD><C2BC><EFBFBD><EFBFBD>ʱ<EFBFBD>䣨<EFBFBD>֣<EFBFBD>max 720<32><30>
#define REVERSE_FR_MIN MEM_ADDR_REG_0XA0 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>3λС<CEBB><D0A1><EFBFBD><EFBFBD>*
#define REVERSE_FR_MIN_L MEM_ADDR_REG_0XA1
#define REVERSE_FR_MAX MEM_ADDR_REG_0XA2 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>3λС<CEBB><D0A1><EFBFBD><EFBFBD>*
#define REVERSE_FR_MAX_L MEM_ADDR_REG_0XA3
#define I2C_ADDR MEM_ADDR_REG_0XA4 // I2C<32><43>ַ
#define I2C_CRC_MOD MEM_ADDR_REG_0XA5 // I2C<32><43>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>crcģʽ(0Ϊ<30><CEAA>crcģʽ)<29><>λ<EFBFBD><CEBB>Ч
#define TIMING_TXD_START MEM_ADDR_REG_0XA6 // <20><>ʱ<EFBFBD><CAB1><EFBFBD>Ϳ<EFBFBD>ʼ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
#define TIMING_TXD_LEN MEM_ADDR_REG_0XA7 // <20><>ʱ<EFBFBD><CAB1><EFBFBD>ͼĴ<CDBC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define TIMING_TXD_TIME MEM_ADDR_REG_0XA8 // <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
#define PRESSURE_OFFSET MEM_ADDR_REG_0XA9 // ѹ<><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define LORA_ADR MEM_ADDR_REG_0XAA // LORA <20><>ַ
#define LORA_NETID MEM_ADDR_REG_0XAB // LORA<52><41>·id
#define LORA_CH MEM_ADDR_REG_0XAC // LORA<52>ŵ<EFBFBD>
#define LORA_STATE MEM_ADDR_REG_0XAD // LORAģ<41>鹤<EFBFBD><E9B9A4>״̬
#define KEY_PASSWORD MEM_ADDR_REG_0XAE // <20><><EFBFBD>ð<EFBFBD><C3B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define KEY_PASSWORD_L MEM_ADDR_REG_0XAF // <20><><EFBFBD>ð<EFBFBD><C3B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define ALARM_UPPER_PRESS MEM_ADDR_REG_0XB0 // ѹ<><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define ALARM_UPPER_PRESS_L MEM_ADDR_REG_0XB1 //
#define ALARM_LOWER_PRESS MEM_ADDR_REG_0XB2 // ѹ<><D1B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define ALARM_LOWER_PRESS_L MEM_ADDR_REG_0XB3 //
#define ALARM_UPPER_TEMP MEM_ADDR_REG_0XB4 // <20><EFBFBD><C2B6><EFBFBD><EFBFBD>ޱ<EFBFBD><DEB1><EFBFBD> B4
#define ALARM_LOWER_TEMP MEM_ADDR_REG_0XB5 // <20><EFBFBD><C2B6><EFBFBD><EFBFBD>ޱ<EFBFBD><DEB1><EFBFBD> B5
#define ALARM_UPPER_RH MEM_ADDR_REG_0XB6 // ʪ<><CAAA><EFBFBD><EFBFBD><EFBFBD>ޱ<EFBFBD><DEB1><EFBFBD> B6
#define ALARM_LOWER_RH MEM_ADDR_REG_0XB7 // ʪ<><CAAA><EFBFBD><EFBFBD><EFBFBD>ޱ<EFBFBD><DEB1><EFBFBD> B7
#define ALARM_UPPER_PPM MEM_ADDR_REG_0XB8 // Ũ<><C5A8><EFBFBD><EFBFBD><EFBFBD>ޱ<EFBFBD><DEB1><EFBFBD> B8
#define ALARM_LOWER_PPM MEM_ADDR_REG_0XB9 // Ũ<><C5A8><EFBFBD><EFBFBD><EFBFBD>ޱ<EFBFBD><DEB1><EFBFBD> B9
//#define BA MEM_ADDR_REG_0XBA //
//#define BB MEM_ADDR_REG_0XBB //
//#define BC MEM_ADDR_REG_0XBC //
//#define BD MEM_ADDR_REG_0XBD //
//#define BE MEM_ADDR_REG_0XBE //
//#define BF MEM_ADDR_REG_0XBF //
//#define C0 MEM_ADDR_REG_0XC0 //
//#define C1 MEM_ADDR_REG_0XC1
//#define C2 MEM_ADDR_REG_0XC2 //
//#define C3 MEM_ADDR_REG_0XC3
//#define C4 MEM_ADDR_REG_0XC4 //
//#define C5 MEM_ADDR_REG_0XC5 //
//#define C6 MEM_ADDR_REG_0XC6 //
//#define C7 MEM_ADDR_REG_0XC7 //
//#define C8 MEM_ADDR_REG_0XC8 //
//#define C9 MEM_ADDR_REG_0XC9 //
//#define CA MEM_ADDR_REG_0XCA //
//#define CB MEM_ADDR_REG_0XCB //
//#define CC MEM_ADDR_REG_0XCC //
//#define CD MEM_ADDR_REG_0XCD //
//#define CE MEM_ADDR_REG_0XCE //
//#define CF MEM_ADDR_REG_0XCF //
//#define D0 MEM_ADDR_REG_0XD0 //
//#define D1 MEM_ADDR_REG_0XD1 //
//#define D2 MEM_ADDR_REG_0XD2 //
//#define D3 MEM_ADDR_REG_0XD3 //
//#define D4 MEM_ADDR_REG_0XD4 //
//#define D5 MEM_ADDR_REG_0XD5 //
//#define D6 MEM_ADDR_REG_0XD6 //
//#define D7 MEM_ADDR_REG_0XD7 //
//#define D8 MEM_ADDR_REG_0XD8 //
//#define D9 MEM_ADDR_REG_0XD9 //
//#define LEAK_FR_MIN MEM_ADDR_REG_0XDA
//#define LEAK_FR_MAX MEM_ADDR_REG_0XDB
//#define LEAK_TIMING MEM_ADDR_REG_0XDC
// //
//#define DD MEM_ADDR_REG_0XDD //
//#define GCF_A MEM_ADDR_REG_0XDE //
//#define DF MEM_ADDR_REG_0XDF //
//#define E0 MEM_ADDR_REG_0XE0 //
//#define E1 MEM_ADDR_REG_0XE1 //
//#define E2 MEM_ADDR_REG_0XE2 //
//#define E3 MEM_ADDR_REG_0XE3 //
//#define E4 MEM_ADDR_REG_0XE4 //
//#define E5 MEM_ADDR_REG_0XE5 //
//#define E6 MEM_ADDR_REG_0XE6 //
//#define E7 MEM_ADDR_REG_0XE7 //
//#define E8 MEM_ADDR_REG_0XE8 //
//#define E9 MEM_ADDR_REG_0XE9 //
//#define EA MEM_ADDR_REG_0XEA //
//#define EB MEM_ADDR_REG_0XEB //
//#define EC MEM_ADDR_REG_0XEC //
//#define ED MEM_ADDR_REG_0XED //
//#define EE MEM_ADDR_REG_0XEE //
//#define EF MEM_ADDR_REG_0XEF //
#define DCOEF_NUM MEM_ADDR_REG_0X130
#endif
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