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CHJ/user/MCU/lhl_adc.c

557 lines
28 KiB
C
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NULL
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#include "../main/SystemInclude.h"
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/*<2A><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼Դ */
static void ADC_REF_Init(u8 vref,u8 vdrive)
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{
REF_InitTypeDef REF_InitStructure;
REF_InitStructure.VREF = vref; // <20>ڲ<EFBFBD><DAB2><EFBFBD>׼<EFBFBD><D7BC>ѹ
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REF_InitStructure.VDRIVE = vdrive;//VDrive<76><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѹ
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REF_InitStructure.VREF_Boost = DISABLE;
LHL_REF_Init(&REF_InitStructure);
}
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static void ADC_Init(ADC_ID_t ADCx ,u8 SPS ,u8 Gain, u8 PChan, u8 NChan )
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{
ADC_InitTypeDef ADC_InitStructure;
ADC_InitStructure.AINP = PChan; // ADC0<43><30><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
ADC_InitStructure.AINM = NChan;
ADC_InitStructure.PGA = Gain; // <20>ڲ<EFBFBD>PGA<47><41><EFBFBD><EFBFBD>x1
ADC_InitStructure.FS = SPS; // ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_InitStructure.Code = ADC_CODE_BIPOLAR; // ˫<><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_InitStructure.Mode = ADC_MODE_CONTINUOUS_CONVERSION; // <20><><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>ģʽ
ADC_InitStructure.Trigger = ADC_TRIGGER_SOFTWARE; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_InitStructure.ReferenceSelect = ADC_REF_REFP_to_REFN; // <20>ڲ<EFBFBD><DAB2><EFBFBD>׼
ADC_InitStructure.REF_BUFP = ENABLE; // ʹ<>ܻ<EFBFBD>׼<EFBFBD><D7BC><EFBFBD><EFBFBD>
ADC_InitStructure.REF_BUFM = ENABLE;
ADC_InitStructure.REF_Precharge= DISABLE;
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ADC_InitStructure.Reference = 2500.0f;
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LHL_ADC_Init(ADCx, &ADC_InitStructure);
}
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static void ADC_SyncInit(u8 SPS ,u8 Gain0, u8 PChan0, u8 NChan0 ,u8 Gain1, u8 PChan1, u8 NChan1 )
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{
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ADC_InitTypeDef ADC_InitStructure;
ADC_InitStructure.AINP = PChan0; // ADC0<43><30><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
ADC_InitStructure.AINM = NChan0;
ADC_InitStructure.PGA = Gain0; // <20>ڲ<EFBFBD>PGA<47><41><EFBFBD><EFBFBD>x1
ADC_InitStructure.FS = SPS; // ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_InitStructure.Code = ADC_CODE_BIPOLAR; // ˫<><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_InitStructure.Mode = ADC_MODE_CONTINUOUS_CONVERSION; // <20><><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>ģʽ
ADC_InitStructure.Trigger = ADC_TRIGGER_SOFTWARE; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_InitStructure.ReferenceSelect = ADC_REF_REFP_to_REFN; // <20>ڲ<EFBFBD><DAB2><EFBFBD>׼
ADC_InitStructure.REF_BUFP = ENABLE; // ʹ<>ܻ<EFBFBD>׼<EFBFBD><D7BC><EFBFBD><EFBFBD>
ADC_InitStructure.REF_BUFM = ENABLE;
ADC_InitStructure.REF_Precharge= DISABLE;
ADC_InitStructure.Reference = 2500.0f;
LHL_ADC_Init(ADC_0, &ADC_InitStructure);
ADC_InitStructure.AINP = PChan1; // ADC1<43><31><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
ADC_InitStructure.AINM = NChan1;
ADC_InitStructure.PGA = Gain1; // <20>ڲ<EFBFBD>PGA<47><41><EFBFBD><EFBFBD>x1
LHL_ADC_Init(ADC_1, &ADC_InitStructure); // ͬ<><CDAC>ģʽ<C4A3>£<EFBFBD>ADC1<43><31>ADC0<43><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬ
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}
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/*********************************************************************************************************************************************/
/*<2A>жϷ<D0B6>ʽ*/
/*********************************************************************************************************************************************/
//ADC0<43><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>----------------------------------------------------------
void ADC0_Conversion_Init(ADC_Config_TypeDef adc_config)
{
ADC_REF_Init(REF_INTERNAL_2P5V,REF_INTERNAL_2P5V);/* 1. <20><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼Դ */
ADC_Init(ADC_0, adc_config.SPS, adc_config.Gain0, adc_config.PChan0, adc_config.NChan0); /* 2. <20><>ʼ<EFBFBD><CABC>ADC0 */
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}
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//ADC1<43><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>----------------------------------------------------------
void ADC1_Conversion_Init(ADC_Config_TypeDef adc_config)
{
ADC_REF_Init(REF_INTERNAL_2P5V,REF_INTERNAL_2P5V);/* 1. <20><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼Դ */
ADC_Init(ADC_1, adc_config.SPS, adc_config.Gain1, adc_config.PChan1, adc_config.NChan1); /* 2. <20><>ʼ<EFBFBD><CABC>ADC1 */
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}
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//ADCͬ<43><CDAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>----------------------------------------------------------
void ADC0_1_SyncConversion_Init(ADC_Config_TypeDef adc_config)
{
ADC_REF_Init(REF_INTERNAL_2P5V,REF_INTERNAL_2P5V); /* 1. <20><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼Դ */
ADC_SyncInit(adc_config.SPS,adc_config.Gain0,adc_config.PChan0,adc_config.NChan0,
adc_config.Gain1,adc_config.PChan1,adc_config.NChan1); /* 2. <20><>ʼ<EFBFBD><CABC>ADC0<43><30>ADC1 */
/* 3. ʹ<><CAB9>ADC<44><43>ͬ<EFBFBD><CDAC>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬ<EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD>֤ADC0<EFBFBD><EFBFBD>ADC1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʣ<EFBFBD>ת<EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȫ<EFBFBD><EFBFBD>ͬ<EFBFBD><EFBFBD>
* ADC_0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӳ<EFBFBD><EFBFBD>trigger<EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD>õ<EFBFBD>ADC_1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͬʱ<EFBFBD><EFBFBD>ADC_0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><EFBFBD><EFBFBD>ơ<EFBFBD>
*/
LHL_ADC_SetSync(ENABLE);
/* 4. ͬ<><CDAC>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>迪<EFBFBD><E8BFAA>ADC0<43><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ready<64>ж<EFBFBD> */
LHL_ADC_ITConfig(ADC_0, ADC_IT_RDY, ENABLE);
NVIC_EnableIRQ(ADC0_IRQn);
NVIC_SetPriority(ADC0_IRQn, 0);
/* 5. <20><><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>迪<EFBFBD><E8BFAA>ADC0 */
LHL_ADC_Start(ADC_0);
}
//ADC <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>24λADC<44><43><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>16λ<36><CEBB><EFBFBD><EFBFBD>ƫ<EFBFBD><C6AB>32768
u32 ADC_ReadSampleData(ADC_ID_t ADCx)
NULL
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{
volatile u32 reg_data = 0;
reg_data = (ADCx == ADC_0) ? LHL_ADC_GetData(ADC_0) : LHL_ADC_GetData(ADC_1);
reg_data = ((((reg_data & 0xFFFFFF) | ((reg_data & 0x800000) ? 0xFF000000 : 0)) >> 8) + 32768) & 0xFFFF;
return reg_data ;
}
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////<2F><>ʼת<CABC><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>---------------------------------------------------------------
//void StartADCConversion(ADC_ID_t ADCx)
//{
// (ADCx == ADC_0) ? LHL_ADC_Start(ADC_0): LHL_ADC_Start(ADC_1);
//}
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//ֹͣת<D6B9><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>---------------------------------------------------------------
void StopADCConversion(ADC_ID_t ADCx)
{
(ADCx == ADC_0) ? LHL_ADC_Stop(ADC_0): LHL_ADC_Stop(ADC_1);
}
NULL
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NULL
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/*********************************************************************************************************************************************/
/*DMA <20><>ʽ һ<><D2BB><EFBFBD>÷<EFBFBD><C3B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC<44><43>*/
/*********************************************************************************************************************************************/
#define MAX_ADC_COUNT 10
typedef struct {
uint32_t BufferA[MAX_ADC_COUNT];//MAX_ADC_COUNT ÿ<>ΰ<EFBFBD><CEB0><EFBFBD>ADC<44><43><EFBFBD><EFBFBD> ADC_SPS_977<37><37><EFBFBD><EFBFBD>1msһ<73><D2BB><EFBFBD><EFBFBD><EFBFBD>ܼ<EFBFBD>10ms <20><>
uint32_t BufferB[MAX_ADC_COUNT];
} ADC_DATA_t; /* ˫<><CBAB><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>ADC<44><43><EFBFBD><EFBFBD>Ϊת<CEAA><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32> */
ADC_DATA_t adcData0 , adcData1;//
__RW uint8_t adcFlag0 , adcFlag1;//DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>־
//<2F><><EFBFBD><EFBFBD>׼<EFBFBD><D7BC><EFBFBD>뿪ʼת<CABC><D7AA>---------------------------------------------------------------
void DMA_ADC0_Conversion_Init(uint8_t Gain0, uint8_t PChan0, uint8_t NChan0)
NULL
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{
NULL
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DMA_HandleTypeDef DMA_Handle_ADC0;
/* 1.1 <20><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼ */
ADC_REF_Init(REF_INTERNAL_2P5V,REF_INTERNAL_2P5V);
/* 1.2 <20><>ʼ<EFBFBD><CABC>ADC */
ADC_Init(ADC_0, SPS_977, Gain0, PChan0, NChan0);
/* 1.3 ʹ<><CAB9>ADC0<43><30>DMA<4D><41><EFBFBD><EFBFBD> */
LHL_ADC_DMACmd(ADC_0, ENABLE);
DMA_DMAMUX_CFG(DMA_CHANNEL_2 ,REQUEST_SOURCE_ADC0);
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/* 2.2 <20><><EFBFBD><EFBFBD>DMAͨ<41><CDA8>0 */
DMA_Handle_ADC0.Channel = DMA_CHANNEL_2;
DMA_Handle_ADC0.Mode = DMA_DIRECT_MODE; // Direct Mode
DMA_Handle_ADC0.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADC0.Init.Direction = DMA_PERIPH_TO_MEMORY; // <20><><EFBFBD><EFBFBD>-><3E>ڴ<EFBFBD>
DMA_Handle_ADC0.Init.Src_Address = (uint32_t)(&ADC->ADC_DATA_0);
DMA_Handle_ADC0.Init.Dest_Address = (uint32_t)&adcData0;
DMA_Handle_ADC0.Init.Data_Width = DMA_DATA_WIDTH_4B;
DMA_Handle_ADC0.Init.Data_Size = 1;
DMA_Handle_ADC0.Init.Repetition = MAX_ADC_COUNT*2; // ˫<><CBAB><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˫<EFBFBD><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DMA_Handle_ADC0.Init.Trans_Mode = DMA_CYCLIC_TRANSMISSION; // ѭ<><D1AD>ģʽ
if (LHL_DMA_Init(&DMA_Handle_ADC0) != LHL_OK)
{
while(1); // DMA Init Error
}
/* 2.3 ʹ<><CAB9>DMA<4D>жϲ<D0B6><CFB2><EFBFBD><EFBFBD><EFBFBD>*/
LHL_DMA_ITConfig(&DMA_Handle_ADC0, DMA_IT_MAJOR | DMA_IT_HALF, ENABLE); // ˫<><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>뿪<EFBFBD><EBBFAA><EFBFBD><EFBFBD><EFBFBD>жϺ<D0B6><CFBA><EFBFBD><EFBFBD>ж<EFBFBD>
NVIC_EnableIRQ(DMA1_CH2_CH3_IRQn);
LHL_DMA_Start(&DMA_Handle_ADC0);
memset(&adcData0, 0, sizeof(adcData0));
adcFlag0 = 0;
LHL_ADC_Start(ADC_0); // <20><><EFBFBD><EFBFBD>ADC0<43><30>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}
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NULL
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void DMA_ADC0_1_SyncConversion_Init(uint8_t Gain0, uint8_t PChan0, uint8_t NChan0 ,uint8_t Gain1, uint8_t PChan1, uint8_t NChan1 )
{
DMA_HandleTypeDef DMA_Handle_ADC0 , DMA_Handle_ADC1;
ADC_REF_Init(REF_INTERNAL_2P5V,REF_INTERNAL_2P5V); /* 1. <20><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼Դ */
ADC_SyncInit(SPS_977,Gain0,PChan0,NChan0,Gain1,PChan1,NChan1); /* 2. <20><>ʼ<EFBFBD><CABC>ADC0<43><30>ADC1 */
LHL_ADC_SetSync(ENABLE); // ͬ<><CDAC>ģʽ
LHL_ADC_DMACmd(ADC_0, ENABLE);// ʹ<><CAB9>ADC0<43><30>ADC1<43><31>DMA<4D><41><EFBFBD><EFBFBD>
LHL_ADC_DMACmd(ADC_1, ENABLE);
/* 3.1 <20><><EFBFBD><EFBFBD>DMAUX<55><58>DMAͨ<41><CDA8>0<EFBFBD><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>ADC0 */
DMA_DMAMUX_CFG(DMA_CHANNEL_2,REQUEST_SOURCE_ADC0);//<2F><>DMAMUX<55><58><EFBFBD>ӵ<EFBFBD>DMAͨ<41><CDA8>
/* 3.2 <20><><EFBFBD><EFBFBD>DMAͨ<41><CDA8>0 */
DMA_Handle_ADC0.Channel = DMA_CHANNEL_2;
DMA_Handle_ADC0.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADC0.Mode = DMA_DIRECT_MODE;
DMA_Handle_ADC0.Init.Direction = DMA_PERIPH_TO_MEMORY; // <20><><EFBFBD><EFBFBD>-><3E>ڴ<EFBFBD>
DMA_Handle_ADC0.Init.Src_Address = (uint32_t)(&pADC->ADC_DATA_0);
DMA_Handle_ADC0.Init.Dest_Address = (uint32_t)&adcData0;
DMA_Handle_ADC0.Init.Data_Width = DMA_DATA_WIDTH_4B;
DMA_Handle_ADC0.Init.Data_Size = 1; // ÿ<><C3BF>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DMA_Handle_ADC0.Init.Repetition = MAX_ADC_COUNT*2; // <20><>ѭ<EFBFBD><D1AD>10<31><30>
DMA_Handle_ADC0.Init.Trans_Mode = DMA_CYCLIC_TRANSMISSION; // ѭ<><D1AD>ģʽ
if (LHL_DMA_Init(&DMA_Handle_ADC0) != LHL_OK)
{
while(1); // DMA Init Error
}
LHL_DMA_ITConfig(&DMA_Handle_ADC0, DMA_IT_MAJOR | DMA_IT_HALF, ENABLE); // <20><><EFBFBD><EFBFBD>DMA0<41><30><EFBFBD>ж<EFBFBD>
NVIC_EnableIRQ(DMA1_CH2_CH3_IRQn);
/* 4.1 <20><><EFBFBD><EFBFBD>DMAUX<55><58>DMAͨ<41><CDA8>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>ADC1 */
DMA_DMAMUX_CFG(DMA_CHANNEL_3,REQUEST_SOURCE_ADC1);//<2F><>DMAMUX<55><58><EFBFBD>ӵ<EFBFBD>DMAͨ<41><CDA8>
/* 4.2 <20><><EFBFBD><EFBFBD>DMAͨ<41><CDA8>1 */
DMA_Handle_ADC1.Channel = DMA_CHANNEL_3;
DMA_Handle_ADC1.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADC1.Mode = DMA_DIRECT_MODE;
DMA_Handle_ADC1.Init.Direction = DMA_PERIPH_TO_MEMORY;
DMA_Handle_ADC1.Init.Src_Address = (uint32_t)(&pADC->ADC_DATA_1); // <20><>ΪADC DATA 1
DMA_Handle_ADC1.Init.Dest_Address = (uint32_t)&adcData1;
DMA_Handle_ADC1.Init.Data_Width = DMA_DATA_WIDTH_4B;
DMA_Handle_ADC1.Init.Data_Size = 1;
DMA_Handle_ADC1.Init.Repetition = MAX_ADC_COUNT*2;
DMA_Handle_ADC1.Init.Trans_Mode = DMA_CYCLIC_TRANSMISSION;
if (LHL_DMA_Init(&DMA_Handle_ADC1) != LHL_OK)
{
while(1); // DMA Init Error
}
LHL_DMA_ITConfig(&DMA_Handle_ADC1, DMA_IT_MAJOR | DMA_IT_HALF, ENABLE);
NVIC_EnableIRQ(DMA1_CH2_CH3_IRQn);
/* 5 ʹ<><CAB9>DMA0<41><30>DMA1*/
LHL_DMA_Start(&DMA_Handle_ADC0);
LHL_DMA_Start(&DMA_Handle_ADC1);
adcFlag0 = 0;
adcFlag1 = 0;
LHL_ADC_Start(ADC_0); // <20><><EFBFBD><EFBFBD>ADC0<43><30>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}
NULL
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NULL
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/* <20><><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>ADC0<43><30>ʼ<EFBFBD>Զ<EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ÿ<EFBFBD><C3BF>ADC0ת<30><D7AA><EFBFBD><EFBFBD><EFBFBD>ɣ<EFBFBD><C9A3><EFBFBD><EFBFBD><EFBFBD>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD>adcData
* <EFBFBD><EFBFBD>DMA0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴﵽ10<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>򴥷<EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴﵽ20<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>򴥷<EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><EFBFBD>Զ<EFBFBD>ֹͣ<EFBFBD><EFBFBD><EFBFBD>ȴ<EFBFBD><EFBFBD>ٴδ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
NULL
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NULL
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/* <20><>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD>ADC0<43><30>ADC1<43><31>ʼͬ<CABC><CDAC>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>
* <EFBFBD><EFBFBD>DMACH0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴﵽ10<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>򴥷<EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>A<EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMACH1ͬ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>10<EFBFBD><EFBFBD>ADC1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>
* <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴﵽ20<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>򴥷<EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݴ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>B<EFBFBD><EFBFBD><EFBFBD><EFBFBD>*/
//<2F><>ADC<44><43><EFBFBD><EFBFBD>---------------------------------------------------------------
uint32_t DMA_ADC_ReadData(uint8_t ADCx)
{
volatile uint32_t reg_data = 0;
uint32_t* buffer_ptr = NULL;
ADC_DATA_t* adc_data ;
uint8_t flag = 0;
NULL
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NULL
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if(ADCx == ADC_0) { flag = adcFlag0; adcFlag0 = 0;} //<2F><><EFBFBD><EFBFBD>ȫ<EFBFBD>ֱ<EFBFBD>־
else if(ADCx == ADC_1){ flag = adcFlag1; adcFlag1 = 0;} //<2F><><EFBFBD><EFBFBD>ȫ<EFBFBD>ֱ<EFBFBD>־
else return 0; // û<>и<EFBFBD>ADC
if (flag == 0) return 0;// û<><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
adc_data = (ADCx == ADC_0) ? &adcData0 : &adcData1;//ѡ<><D1A1>ADC<44><43><EFBFBD><EFBFBD>Դ/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
buffer_ptr = (flag == 1) ? adc_data->BufferA : adc_data->BufferB;//flag=1<><31><EFBFBD>ж<EFBFBD> flag=2ȫ<32>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>
for(uint8_t i = 0; i < MAX_ADC_COUNT; i++)
{
buffer_ptr[i] = ((((buffer_ptr[i] & 0xFFFFFF) | ((buffer_ptr[i] & 0x800000) ? 0xFF000000 : 0)) >> 8) + 32768) & 0xFFFF;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>16λ<36><CEBB><EFBFBD><EFBFBD>
reg_data += buffer_ptr[i];//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĺ<EFBFBD>
}
reg_data = reg_data / MAX_ADC_COUNT;//<2F><>ƽ<EFBFBD><C6BD>
return reg_data ;
}
/*********************************************************************************************************************************************/
/*DMA <20><><EFBFBD>з<EFBFBD>ʽ */
/*********************************************************************************************************************************************/
#if 1 //DMA_ADC<44><43><EFBFBD>з<EFBFBD>ʽ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD>ȡ
//Channel Sequencer =========================================================================
__RW uint8_t adcFlag;//DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>־
#define SEQUENCER_COUNT 4 //<2F><><EFBFBD><EFBFBD>ADC_MAX_SEQUENCER_CHANNELS
// ADC0<43><30><EFBFBD>ñ<EFBFBD> - <20><><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
static const SeqChannelConfig ADC0seq_configs[SEQUENCER_COUNT] = {
{ADC0_AINP_AIN0, ADC0_AINM_AVSS}, // Seq0
{ADC0_AINP_AIN1, ADC0_AINM_AIN0}, // Seq1
{ADC0_AINP_AIN2, ADC0_AINM_AIN1}, // Seq2
{ADC0_AINP_AIN3, ADC0_AINM_AIN2}, // Seq3
// {ADC0_AINP_AIN4, ADC0_AINM_AIN3}, // Seq4
// {ADC0_AINP_AIN5, ADC0_AINM_AIN4}, // Seq5
// {ADC0_AINP_AIN6, ADC0_AINM_AIN5}, // Seq6
// {ADC0_AINP_AIN7, ADC0_AINM_AIN6}, // Seq7
};
// ADC1<43><31><EFBFBD>ñ<EFBFBD> - <20><><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
static const SeqChannelConfig ADC1seq_configs[SEQUENCER_COUNT] = {
{ADC1_AINP_AIN0, ADC1_AINM_AVSS}, // Seq0
{ADC1_AINP_AIN1, ADC1_AINM_AIN0}, // Seq1
{ADC1_AINP_AIN2, ADC1_AINM_AIN1}, // Seq2
{ADC1_AINP_AIN3, ADC1_AINM_AIN2}, // Seq3
// {ADC1_AINP_AIN4, ADC1_AINM_AIN3}, // Seq4
// {ADC1_AINP_AIN5, ADC1_AINM_AIN4}, // Seq5
// {ADC1_AINP_AIN6, ADC1_AINM_AIN5}, // Seq6
// {ADC1_AINP_AIN7, ADC1_AINM_AIN6}, // Seq7
};
/* <20><><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<43><30><EFBFBD><EFBFBD>
* ==<EFBFBD><EFBFBD>ADCת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>
* ==<EFBFBD><EFBFBD>DMA0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* ==<EFBFBD><EFBFBD>DMA1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD>ADC0<EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* ==<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCͨ<EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹͣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA1<EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD> */
ADC_Data_t adcBuffer[SEQUENCER_COUNT]; /* <20><>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
void DMA_ADC0_SingleChannel_Init(void)
NULL
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{
NULL
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ADC_InitTypeDef ADC_InitStructure;
ADC_SingleCSInitTypeDef ADC_CSInitStructure; /* <20><>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD>ṹ<EFBFBD><E1B9B9> */
ADC_Config_t ADC_Config[SEQUENCER_COUNT] __ALIGN(32); /* <20><>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>32λ<32><CEBB><EFBFBD><EFBFBD> */
DMAMUX_InitTypeDef DMAMUX_InitStructure;
DMA_HandleTypeDef DMA_Handle_ADCstatus ,DMA_Handle_ADCcontrol;
/* 1. <20><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼ */
ADC_REF_Init(REF_INTERNAL_2P5V,REF_INTERNAL_2P5V);
/* 2.1 <20><>ʼ<EFBFBD><CABC>ADC0<43><30>ADC1ͨ<31><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCͨ<43>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̶<EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>
* Ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽר<EFBFBD>ýṹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˳<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ */
ADC_InitStructure.FS = ADC_SPS_12P5; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>12.5SPS<EFBFBD><EFBFBD>4ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѯ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>1SPS<EFBFBD><EFBFBD>
ADC_InitStructure.PGA = ADC_PGA_GAIN_1;
ADC_InitStructure.Code = ADC_CODE_BIPOLAR;
ADC_InitStructure.ReferenceSelect = ADC_REF_REFP_to_REFN;
ADC_InitStructure.REF_BUFP = ENABLE;
ADC_InitStructure.REF_BUFM = ENABLE;
ADC_InitStructure.REF_Precharge = DISABLE;
ADC_InitStructure.Reference = 2500.0f;
ADC_CSInitStructure.ADC_ID = ADC_0; // ADC0
ADC_CSInitStructure.ADC_CFG = ADC_Config; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_CSInitStructure.Active_Channels = SEQUENCER_COUNT; // <20><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_CSInitStructure.Cycle_Mode = DISABLE; // ѭ<><D1AD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD><D0BA>ȴ<EFBFBD><C8B4>´δ<C2B4><CEB4><EFBFBD><EFBFBD><EFBFBD>
ADC_CSInitStructure.Sequencer_Trigger = ADC_TRIGGER_SOFTWARE; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>ֹͣ<CDA3><D6B9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD>βɼ<CEB2>һ<EFBFBD><D2BB>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>
for (int i = 0; i < SEQUENCER_COUNT; i++) { //SEQUENCER_COUNT =4: ADC0<43><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>0->1->2->3->0->1->...
ADC_CSInitStructure.AINP_Channel[i] = ADC0seq_configs[i].ainp_channel;
ADC_CSInitStructure.AINM_Channel[i] = ADC0seq_configs[i].ainm_channel;
}
LHL_ADC_SingleChannelSequencerInit(&ADC_InitStructure, &ADC_CSInitStructure);
/* 2.2 ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD>ӦADC<44><43>DMA<4D><41><EFBFBD><EFBFBD> */
LHL_ADC_DMACmd(ADC_0, ENABLE); // ʹ<><CAB9>ADC0<43><30>DMA<4D><41><EFBFBD><EFBFBD>
/* 3.1 <20><><EFBFBD><EFBFBD>DMAUX<55><58>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>ADC0 */
DMA_DMAMUX_CFG(DMA_CHANNEL_0 ,REQUEST_SOURCE_ADC0);
/* 3.2 <20><><EFBFBD><EFBFBD>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD>ڶ<EFBFBD>ȡADC0<43><30><EFBFBD>ݺ<EFBFBD>״̬ */
DMA_Handle_ADCstatus.Channel = DMA_CHANNEL_0; // <20><><EFBFBD><EFBFBD>hDMA0
DMA_Handle_ADCstatus.Mode = DMA_CHAINING_MODE;
DMA_Handle_ADCstatus.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADCstatus.Init.Direction = DMA_PERIPH_TO_MEMORY;
DMA_Handle_ADCstatus.Init.Src_Address = (uint32_t)(&pADC->ADC_STATUS_0); // Դ<><D4B4>ַ<EFBFBD><D6B7>ȡADC0<43><30><EFBFBD><EFBFBD>
DMA_Handle_ADCstatus.Init.Dest_Address = (uint32_t)adcBuffer;
DMA_Handle_ADCstatus.Init.Data_Width = DMA_DATA_WIDTH_4B;
DMA_Handle_ADCstatus.Init.Data_Size = 2; // ״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD>ݹ<EFBFBD>2<EFBFBD><32><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
DMA_Handle_ADCstatus.Init.Repetition = SEQUENCER_COUNT;
DMA_Handle_ADCstatus.Init.Trans_Mode = DMA_CYCLIC_TRANSMISSION;
DMA_Handle_ADCstatus.Init.Chaining = TO_DMA_CHANNEL_1; // <20><><EFBFBD>ɺ<EFBFBD><C9BA>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>DMA1
if (LHL_DMA_Init(&DMA_Handle_ADCstatus) != LHL_OK)
{
while(1); // DMA Init Error
}
/* 4.1 <20><><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<43><30>ͨ<EFBFBD><CDA8><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> */
DMA_Handle_ADCcontrol.Channel = DMA_CHANNEL_1; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>->hDMA1
DMA_Handle_ADCcontrol.Mode = DMA_DIRECT_MODE;
DMA_Handle_ADCcontrol.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADCcontrol.Init.Direction = DMA_MEMORY_TO_PERIPH;
DMA_Handle_ADCcontrol.Init.Src_Address = (uint32_t)ADC_Config; // Դ<><D4B4>ַ<EFBFBD><D6B7>ȡADC0ͨ<30><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD>
DMA_Handle_ADCcontrol.Init.Dest_Address = (uint32_t)(&pADC->ADC_CONTROL_0); // Ŀ<>ĵ<EFBFBD>ַ<EFBFBD><D6B7>ADC0<43>Ĵ<EFBFBD><C4B4><EFBFBD>
DMA_Handle_ADCcontrol.Init.Data_Width = DMA_DATA_WIDTH_4B;
DMA_Handle_ADCcontrol.Init.Data_Size = 2;
DMA_Handle_ADCcontrol.Init.Repetition = SEQUENCER_COUNT;
DMA_Handle_ADCcontrol.Init.Trans_Mode = DMA_CYCLIC_TRANSMISSION;
if (LHL_DMA_Init(&DMA_Handle_ADCcontrol) != LHL_OK)
{
while(1); // DMA Init Error
}
/* 4.2 ʹ<><CAB9>DMA<4D>ж<EFBFBD> */
LHL_DMA_ITConfig(&DMA_Handle_ADCcontrol, DMA_IT_MAJOR, ENABLE);
NVIC_EnableIRQ(DMA1_CH1_IRQn);
/* 5. <20><>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DMA*/
LHL_DMA_Start(&DMA_Handle_ADCstatus);
adcFlag = 0;
memset(&adcBuffer,0,sizeof(adcBuffer));
NULL
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}
NULL
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/* <20><><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><DFBC><EFBFBD> <20><><EFBFBD><EFBFBD>ADC0<43><30><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC>ģʽ<C4A3><CABD>ADC1ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* ==<EFBFBD><EFBFBD>ADCת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<EFBFBD><EFBFBD>ADC1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݡ<EFBFBD>
* ==<EFBFBD><EFBFBD>DMA0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA1<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<EFBFBD><EFBFBD>ADC1<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD>ADCת<EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD>ת<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
typedef struct{ /* ˫ADC<44><43>˫<EFBFBD><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
ADC_DualData_t BufferA[SEQUENCER_COUNT];
ADC_DualData_t BufferB[SEQUENCER_COUNT];
} ADC_DualData_Buffer_t;
ADC_DualData_Buffer_t adcDualBuffer; /* ˫ADC<44><43><EFBFBD><EFBFBD><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD> */
#define TCD_COUNT 2 /* ˫<><CBAB><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
void DMA_ADC0_1_DualChannel_Init(void)
NULL
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{
NULL
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ADC_InitTypeDef ADC_InitStructure;
ADC_DualCSInitTypeDef ADC_DualCSInitStructure; /* ˫ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD>ṹ<EFBFBD><E1B9B9> */
ADC_DualConfig_t ADC_DualConfig[SEQUENCER_COUNT] __ALIGN(128); /* ˫ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>128λ<38><CEBB><EFBFBD><EFBFBD> */
DMAMUX_InitTypeDef DMAMUX_InitStructure;
DMA_HandleTypeDef DMA_Handle_ADCstatus ,DMA_Handle_ADCcontrol;/* <20><><EFBFBD>õ<EFBFBD>2·DMA */
DMA_InitTypeDef DMA_InitStructure[TCD_COUNT]; /* TCD<43><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9> */
DMA_DES_N_TypeDef TCD_Quene[TCD_COUNT] __ALIGN(32); /* DMA TCD<43><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>32λ<32><CEBB><EFBFBD><EFBFBD>*/
/* 1.1 <20><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼ */
ADC_REF_Init(REF_INTERNAL_2P5V,REF_INTERNAL_OFF);
/* 1.2 <20><>ʼ<EFBFBD><CABC>ADC0<43><30>ADC1ͨ<31><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCͨ<43>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>
* Ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽר<EFBFBD>ýṹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD>ţ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><EFBFBD>ģʽ<EFBFBD><EFBFBD><EFBFBD>Լ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ */
ADC_InitStructure.FS = ADC_SPS_12P5; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_InitStructure.PGA = ADC_PGA_GAIN_1;
ADC_InitStructure.Code = ADC_CODE_BIPOLAR;
ADC_InitStructure.ReferenceSelect = ADC_REF_REFP_to_REFN;
ADC_InitStructure.REF_BUFP = ENABLE;
ADC_InitStructure.REF_BUFM = ENABLE;
ADC_InitStructure.REF_Precharge = DISABLE;
ADC_InitStructure.Reference = 2500.0f;
ADC_DualCSInitStructure.ADC_CFGs = ADC_DualConfig; // ˫ͨ<CBAB><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_DualCSInitStructure.Active_Channels = SEQUENCER_COUNT; // <20><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>4<EFBFBD><34>
ADC_DualCSInitStructure.Cycle_Mode = DISABLE; // ѭ<><D1AD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD><D0BA>ȴ<EFBFBD><C8B4>´δ<C2B4><CEB4><EFBFBD><EFBFBD><EFBFBD>
ADC_DualCSInitStructure.Sequencer_Trigger = ADC_TRIGGER_SOFTWARE; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>ֹͣ<CDA3><D6B9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD>βɼ<CEB2>һ<EFBFBD><D2BB>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>
for (int i = 0; i < SEQUENCER_COUNT; i++) {
ADC_DualCSInitStructure.AINP0_Channel[i] = ADC0seq_configs[i].ainp_channel;
ADC_DualCSInitStructure.AINM0_Channel[i] = ADC0seq_configs[i].ainm_channel;
ADC_DualCSInitStructure.AINP1_Channel[i] = ADC1seq_configs[i].ainp_channel;
ADC_DualCSInitStructure.AINM1_Channel[i] = ADC1seq_configs[i].ainm_channel;
}
LHL_ADC_DualChannelSequencerInit(&ADC_InitStructure, &ADC_DualCSInitStructure); // <20><>ʼ<EFBFBD><CABC>ADC˫<43><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
/* 1.3 ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>ͬ<EFBFBD><CDAC>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ӦADC<44><43>DMA<4D><41><EFBFBD><EFBFBD> */
LHL_ADC_SetSync(ENABLE); // <20><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>ͬ<EFBFBD><CDAC>ģʽ
LHL_ADC_DMACmd(ADC_0, ENABLE); // <20><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>ADC0<43><30>ADC1<43><31>DMA<4D><41><EFBFBD><EFBFBD>
LHL_ADC_DMACmd(ADC_1, ENABLE);
/* 2. <20><><EFBFBD><EFBFBD>DMAUX<55><58>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>ADC0 */
DMA_DMAMUX_CFG(DMA_CHANNEL_0 ,REQUEST_SOURCE_ADC0);
/* 3. <20><><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD>ڶ<EFBFBD>ȡADC0<43><30>ADC1<43><31><EFBFBD><EFBFBD><EFBFBD>ݺ<EFBFBD>״̬ */
DMA_Handle_ADCstatus.Channel = DMA_CHANNEL_0; // <20><><EFBFBD><EFBFBD>hDMA0
DMA_Handle_ADCstatus.Mode = DMA_SCATTER_GATHER_MODE; // <20><>ɢ<EFBFBD>ۺ<EFBFBD>ģʽ
DMA_Handle_ADCstatus.Request = DMA_HARDWARE_REQUEST; // Ӳ<><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DMA_Handle_ADCstatus.TCD_Count = TCD_COUNT; // 2<><32>TCD<43><44><EFBFBD><EFBFBD>˫<EFBFBD><CBAB><EFBFBD><EFBFBD>
DMA_Handle_ADCstatus.TCD_List = TCD_Quene; // TCD<43><44><EFBFBD><EFBFBD>
DMA_Handle_ADCstatus.TCD_Init = DMA_InitStructure; // TCD<43><44>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DMA_InitStructure[0].Direction = DMA_PERIPH_TO_MEMORY; // TCD0<44><30><EFBFBD><EFBFBD>ADC0<43><30>ADC1<43><31><EFBFBD><EFBFBD><EFBFBD>ݶ<EFBFBD>ȡ
DMA_InitStructure[0].Src_Address = (uint32_t)(&pADC->IO_CONTROL_IOUT);
DMA_InitStructure[0].Data_Width = DMA_DATA_WIDTH_16B;
DMA_InitStructure[0].Dest_Address = (uint32_t)&adcDualBuffer.BufferA[0];// ָ<>򻺴<EFBFBD><F2BBBAB4><EFBFBD>A
DMA_InitStructure[0].Data_Size = 2;
DMA_InitStructure[0].Repetition = SEQUENCER_COUNT;
DMA_InitStructure[0].Trans_Mode = DMA_INTERVAL_TRANSMISSION; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڶ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڵļĴ<C4BC><C4B4><EFBFBD>
DMA_InitStructure[0].Src_Interval_Factor = 3;
DMA_InitStructure[0].Dest_Interval_Factor = 1;
DMA_InitStructure[0].Chaining = TO_DMA_CHANNEL_1; // <20><>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD><EFBFBD>ADC<44><43><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD>л<EFBFBD>
DMA_InitStructure[0].TCD_Address = (int32_t)&TCD_Quene[1]; // <20><><EFBFBD>ɺ<EFBFBD><C9BA><EFBFBD><EFBFBD><EFBFBD>TCD1<44><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD>
DMA_InitStructure[0].Auto_Start = DISABLE;
DMA_InitStructure[0].INT_Major = DISABLE;
DMA_InitStructure[0].INT_Half = DISABLE;
DMA_InitStructure[1].Direction = DMA_PERIPH_TO_MEMORY; // TCD1<44><31>TCD0<44><30><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>
DMA_InitStructure[1].Src_Address = (uint32_t)(&pADC->IO_CONTROL_IOUT);
DMA_InitStructure[1].Data_Width = DMA_DATA_WIDTH_16B;
DMA_InitStructure[1].Dest_Address = (uint32_t)&adcDualBuffer.BufferB[0];// ָ<>򻺴<EFBFBD><F2BBBAB4><EFBFBD>B
DMA_InitStructure[1].Data_Size = 2;
DMA_InitStructure[1].Repetition = 4;
DMA_InitStructure[1].Trans_Mode = DMA_INTERVAL_TRANSMISSION;
DMA_InitStructure[1].Src_Interval_Factor = 3;
DMA_InitStructure[1].Dest_Interval_Factor = 1;
DMA_InitStructure[1].Chaining = TO_DMA_CHANNEL_1;
DMA_InitStructure[1].TCD_Address = (int32_t)&TCD_Quene[0]; // <20><><EFBFBD>ɺ<EFBFBD><C9BA>ص<EFBFBD>TCD0
DMA_InitStructure[1].Auto_Start = DISABLE;
DMA_InitStructure[1].INT_Major = DISABLE;
DMA_InitStructure[1].INT_Half = DISABLE;
if (LHL_DMA_Init(&DMA_Handle_ADCstatus) != LHL_OK)
{
while(1); // DMA Init Error
}
/* 4. <20><><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<43><30>ADC1<43>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> */
DMA_Handle_ADCcontrol.Channel = DMA_CHANNEL_1; // ע<><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>->hDMA1
DMA_Handle_ADCcontrol.Mode = DMA_DIRECT_MODE;
DMA_Handle_ADCcontrol.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADCcontrol.Init.Direction = DMA_MEMORY_TO_PERIPH;
DMA_Handle_ADCcontrol.Init.Src_Address = (uint32_t)&ADC_DualConfig[0]; // Դ<><D4B4>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC˫ͨ<CBAB><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD>б<EFBFBD>
DMA_Handle_ADCcontrol.Init.Data_Width = DMA_DATA_WIDTH_16B;
DMA_Handle_ADCcontrol.Init.Dest_Address = (uint32_t)(&pADC->INTERRUPT_CONTROL_0); // Ŀ<>ĵ<EFBFBD>ַ<EFBFBD><D6B7>ADC1 CHANNEL_CFG<46>Ĵ<EFBFBD><C4B4><EFBFBD>
DMA_Handle_ADCcontrol.Init.Data_Size = 2;
DMA_Handle_ADCcontrol.Init.Repetition = SEQUENCER_COUNT; // <20><>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>
DMA_Handle_ADCcontrol.Init.Trans_Mode = DMA_INTERVAL_TRANSMISSION;
DMA_Handle_ADCcontrol.Init.Src_Interval_Factor = 1;
DMA_Handle_ADCcontrol.Init.Dest_Interval_Factor = 3;
if (LHL_DMA_Init(&DMA_Handle_ADCcontrol) != LHL_OK)
{
while(1); // DMA Init Error
}
/* 5. <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD>ʹ<EFBFBD><CAB9>DMA1<41>ж<EFBFBD> */
LHL_DMA_ITConfig(&DMA_Handle_ADCcontrol, DMA_IT_MAJOR, ENABLE); // <20><><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD>ж<EFBFBD>
NVIC_EnableIRQ(DMA1_CH1_IRQn);
/* 6. <20><>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DMA0 */
LHL_DMA_Start(&DMA_Handle_ADCstatus);
adcFlag = 0;
memset(&adcDualBuffer,0,sizeof(adcDualBuffer));
NULL
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}
NULL
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//<2F><>ADC<44><43><EFBFBD><EFBFBD>---------------------------------------------------------------
uint32_t ADC_ReadSingleData(uint8_t SeqChannelNum)//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>0-8<><38><EFBFBD><EFBFBD>ȡ
NULL
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{
NULL
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volatile uint32_t reg_data;
if (adcFlag > 0)
NULL
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{
NULL
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reg_data = adcBuffer[SeqChannelNum].ADC_Data ;//24bit<69><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ
reg_data = ((((reg_data & 0xFFFFFF) | ((reg_data & 0x800000) ? 0xFF000000 : 0)) >> 8) + 32768) & 0xFFFF;
adcFlag = 0;
}
return reg_data ;
}
uint32_t ADC_ReadDualData(ADC_ID_t adcx ,uint8_t SeqChannelNum)//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>0-8<><38><EFBFBD><EFBFBD>ȡ
{
volatile uint32_t reg_data;
volatile uint32_t uCurrentBuffer = LHL_DMA_GetDestAddress(DMA_CHANNEL_0); // <20><>ȡDMA0<41><30>ǰָ<C7B0><D6B8><EFBFBD><EFBFBD>Buffer ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>DMA_CHANNEL_0
if (adcFlag > 0)
{
if (uCurrentBuffer < (uint32_t)adcDualBuffer.BufferB) // ͨ<><CDA8><EFBFBD><EFBFBD>ȡDMA0<41><30>Ŀ<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>Buffer
{
//The dual ADC data is stored in BufferB;
if(adcx == ADC_0) reg_data = adcDualBuffer.BufferB[SeqChannelNum].ADC0_Data ;
else reg_data = adcDualBuffer.BufferB[SeqChannelNum].ADC1_Data ;
}
else
{
//The dual ADC data is stored in BufferA
if(adcx == ADC_0) reg_data = adcDualBuffer.BufferA[SeqChannelNum].ADC0_Data ;
else reg_data = adcDualBuffer.BufferA[SeqChannelNum].ADC1_Data ;
}
reg_data = ((((reg_data & 0xFFFFFF) | ((reg_data & 0x800000) ? 0xFF000000 : 0)) >> 8) + 32768) & 0xFFFF;
adcFlag = 0;
}
return reg_data ;
NULL
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}
NULL
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#endif
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