2026-03-20 21:16:58 +08:00
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#ifndef __LHL_ADC_H__
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#define __LHL_ADC_H__
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/*==================================================================================*/
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//ϵͳ<CFB5><CDB3><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>
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/*==================================================================================*/
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2026-03-20 21:19:04 +08:00
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#define ADC pADC
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2026-03-20 21:16:58 +08:00
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//<2F><><EFBFBD><EFBFBD> Gain0 Gain1
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#define GAIN1 ADC_PGA_GAIN_1
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#define GAIN2 ADC_PGA_GAIN_2
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#define GAIN4 ADC_PGA_GAIN_4
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#define GAIN8 ADC_PGA_GAIN_8
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#define GAIN16 ADC_PGA_GAIN_16
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#define GAIN32 ADC_PGA_GAIN_32
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#define GAIN64 ADC_PGA_GAIN_64
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#define GAIN128 ADC_PGA_GAIN_128
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#define GAINPASS ADC_PGA_BYPASS
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//<2F><><EFBFBD><EFBFBD> SPS
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// //typedef enum {
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#define SPS_7813 ADC_SPS_7813 // ADC_SPS_7813 = 0u,
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#define SPS_3906 ADC_SPS_3906 // ADC_SPS_3906,
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#define SPS_1953 ADC_SPS_1953 // ADC_SPS_1953,
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#define SPS_977 ADC_SPS_977 // ADC_SPS_977,
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#define SPS_488 ADC_SPS_488 // ADC_SPS_488,
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#define SPS_244 ADC_SPS_244 // ADC_SPS_244,
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#define SPS_122 ADC_SPS_122 // ADC_SPS_122,
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#define SPS_61 ADC_SPS_61 // ADC_SPS_61,
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#define SPS_60 ADC_SPS_60 // ADC_SPS_60,
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#define SPS_30 ADC_SPS_30 // ADC_SPS_30,
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#define SPS_15 ADC_SPS_15 // ADC_SPS_15,
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#define SPS_50 ADC_SPS_50 // ADC_SPS_50 = 16u,
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#define SPS_25 ADC_SPS_25 // ADC_SPS_25,
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#define SPS_12P5 ADC_SPS_12P5 // ADC_SPS_12P5,
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#define SPS_10 ADC_SPS_10 // ADC_SPS_10 = 24u,
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#define SPS_5 ADC_SPS_5 // ADC_SPS_5,
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#define SPS_2P5 ADC_SPS_2P5 // ADC_SPS_2P5,
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// //} ADC_DATA_RATE_t;
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//<2F><><EFBFBD><EFBFBD> PChan0 NChan0
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// typedef enum { typedef enum {
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#define ADC0_AIN0 ADC0_AINP_AIN0 // ADC0_AINP_AIN0 = 0x00u, ADC0_AINM_AIN0 = 0x00u,
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#define ADC0_AIN1 ADC0_AINP_AIN1 // ADC0_AINP_AIN1, ADC0_AINM_AIN1,
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#define ADC0_AIN2 ADC0_AINP_AIN2 // ADC0_AINP_AIN2, ADC0_AINM_AIN2,
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#define ADC0_AIN3 ADC0_AINP_AIN3 // ADC0_AINP_AIN3, ADC0_AINM_AIN3,
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#define ADC0_AIN4 ADC0_AINP_AIN4 // ADC0_AINP_AIN4, ADC0_AINM_AIN4,
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#define ADC0_AIN5 ADC0_AINP_AIN5 // ADC0_AINP_AIN5, ADC0_AINM_AIN5,
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#define ADC0_AIN6 ADC0_AINP_AIN6 // ADC0_AINP_AIN6, ADC0_AINM_AIN6,
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#define ADC0_AIN7 ADC0_AINP_AIN7 // ADC0_AINP_AIN7, ADC0_AINM_AIN7,
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#define ADC0_AIN8 ADC0_AINP_AIN8 // ADC0_AINP_AIN8, ADC0_AINM_AIN8,
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#define ADC0_AIN9 ADC0_AINP_AIN9 // ADC0_AINP_AIN9, ADC0_AINM_AIN9,
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#define ADC0_AIN10 ADC0_AINP_AIN10 // ADC0_AINP_AIN10, ADC0_AINM_AIN10,
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#define ADC0_AIN11 ADC0_AINP_AIN11 // ADC0_AINP_AIN11, ADC0_AINM_AIN11,
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#define ADC0_AVSS ADC0_AINP_AVSS // ADC0_AINP_AVSS = 0x10u, ADC0_AINM_AVSS = 0x10u,
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#define ADC0_REFP ADC0_AINP_REFP // ADC0_AINP_REFP, ADC0_AINM_REFP,
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#define ADC0_CALIBP ADC0_AINP_CALIBP // ADC0_AINP_CALIBP, ADC0_AINM_CALIBN,
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// } ADC0_AINP_CHANNEL_t; } ADC0_AINM_CHANNEL_t;
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//<2F><><EFBFBD><EFBFBD> PChan1 NChan1
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//typedef enum { typedef enum {
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#define ADC1_AIN0 ADC1_AINP_AIN0 // ADC1_AINP_AIN0 = 0x00u, ADC1_AINM_AIN0 = 0x00u,
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#define ADC1_AIN1 ADC1_AINP_AIN1 // ADC1_AINP_AIN1, ADC1_AINM_AIN1,
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#define ADC1_AIN2 ADC1_AINP_AIN2 // ADC1_AINP_AIN2, ADC1_AINM_AIN2,
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#define ADC1_AIN3 ADC1_AINP_AIN3 // ADC1_AINP_AIN3, ADC1_AINM_AIN3,
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#define ADC1_AIN4 ADC1_AINP_AIN4 // ADC1_AINP_AIN4, ADC1_AINM_AIN4,
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#define ADC1_AIN5 ADC1_AINP_AIN5 // ADC1_AINP_AIN5, ADC1_AINM_AIN5,
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#define ADC1_AIN6 ADC1_AINP_AIN6 // ADC1_AINP_AIN6, ADC1_AINM_AIN6,
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#define ADC1_AIN7 ADC1_AINP_AIN7 // ADC1_AINP_AIN7, ADC1_AINM_AIN7,
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#define ADC1_AIN8 ADC1_AINP_AIN8 // ADC1_AINP_AIN8, ADC1_AINM_AIN8,
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#define ADC1_AIN9 ADC1_AINP_AIN9 // ADC1_AINP_AIN9, ADC1_AINM_AIN9,
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#define ADC1_AIN10 ADC1_AINP_AIN10 // ADC1_AINP_AIN10, ADC1_AINM_AIN10,
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#define ADC1_AIN11 ADC1_AINP_AIN11 // ADC1_AINP_AIN11, ADC1_AINM_AIN11,
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#define ADC1_AINTEMPP ADC1_AINP_TEMPP // ADC1_AINP_TEMPP = 0x10u, ADC1_AINM_TEMPN = 0x10u,
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#define ADC1_AVSS ADC1_AINP_AVSS // ADC1_AINP_AVSS, ADC1_AINM_AVSS,
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#define ADC1_REFP ADC1_AINP_REFP // ADC1_AINP_REFP, ADC1_AINM_REFP,
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#define ADC1_DACP ADC1_AINP_DACP // ADC1_AINP_DACP, ADC1_AINM_DACN,
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#define ADC1_LOOPP ADC1_AINP_LOOPP // ADC1_AINP_LOOPP, ADC1_AINM_LOOPN,
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#define ADC1_AVDDP ADC1_AINP_AVDDP // ADC1_AINP_AVDDP, ADC1_AINM_AVDDN,
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#define ADC1_IOVDDP ADC1_AINP_IOVDDP // ADC1_AINP_IOVDDP, ADC1_AINM_IOVDDN,
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#define ADC1_CALIBP ADC1_AINP_CALIBP // ADC1_AINP_CALIBP, ADC1_AINM_CALIBN,
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//} ADC1_AINP_CHANNEL_t; } ADC1_AINM_CHANNEL_t;
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2026-03-20 21:19:04 +08:00
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2026-03-20 21:16:58 +08:00
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/*==================================================================================*/
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//ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>
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/*==================================================================================*/
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2026-03-20 21:19:04 +08:00
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typedef struct {
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u8 Gain0; //<2F><><EFBFBD><EFBFBD><EFBFBD>Ŵ<EFBFBD>ϵ<EFBFBD><CFB5>
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u8 PChan0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
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u8 NChan0; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
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u8 Gain1; //<2F><><EFBFBD><EFBFBD><EFBFBD>Ŵ<EFBFBD>ϵ<EFBFBD><CFB5>
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u8 PChan1; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
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u8 NChan1; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
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u8 SPS; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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} ADC_Config_TypeDef;
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void ADC0_Conversion_Init(ADC_Config_TypeDef adcCfg);
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void ADC1_Conversion_Init(ADC_Config_TypeDef adcCfg);
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void ADC0_1_SyncConversion_Init(ADC_Config_TypeDef adcCfg);
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//void StartADCConversion(ADC_ID_t ADCx);//ADC_ID_t
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void StopADCConversion(ADC_ID_t ADCx);//ADC_ID_t
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uint32_t ADC_ReadSampleData(ADC_ID_t ADCx);
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extern __RW uint8_t adcFlag0 , adcFlag1;
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2026-03-20 21:16:58 +08:00
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2026-03-20 21:19:04 +08:00
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void DMA_ADC0_Conversion_Init(uint8_t Gain, uint8_t PChan, uint8_t NChan);
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void DMA_ADC0_1_SyncConversion_Init(uint8_t Gain0, uint8_t PChan0, uint8_t NChan0 ,uint8_t Gain1, uint8_t PChan1, uint8_t NChan1 );
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uint32_t DMA_ADC_ReadData(ADC_ID_t ADCx);
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2026-03-20 21:16:58 +08:00
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2026-03-20 21:19:04 +08:00
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typedef struct {
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uint8_t ainp_channel;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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uint8_t ainm_channel; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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}SeqChannelConfig;
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void DMA_ADC_SingleChannel_Init(void);
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2026-03-20 21:16:58 +08:00
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#endif
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