2026-03-20 21:16:58 +08:00
|
|
|
|
#include "../main/SystemInclude.h"
|
|
|
|
|
|
|
|
|
|
|
|
DMA_HandleTypeDef DMA_Handle_UartRx , DMA_Handle_UartTx ;
|
|
|
|
|
|
/*********************************************************************************************************************************************/
|
|
|
|
|
|
/*<2A><>ʼ<EFBFBD><CABC>*/
|
|
|
|
|
|
/*********************************************************************************************************************************************/
|
|
|
|
|
|
void UART0_Init(uint32_t baudrate_bps)
|
|
|
|
|
|
{
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
|
|
|
|
UART_InitTypeDef UART_InitStructure;
|
|
|
|
|
|
|
|
|
|
|
|
/* 1. <20><><EFBFBD><EFBFBD> UART GPIO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|
|
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_1;
|
|
|
|
|
|
GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
|
|
|
|
|
|
GPIO_InitStructure.Current = GPIO_CURRENT_4mA;
|
|
|
|
|
|
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
|
|
|
|
|
GPIO_InitStructure.SchmittTrigger = ENABLE;
|
|
|
|
|
|
GPIO_InitStructure.Alternate = GPIO0_1_AF_SIN0;
|
|
|
|
|
|
LHL_GPIO_Init(pGPIO0, &GPIO_InitStructure); // P0.1 -> SIN0(UART_RX)
|
|
|
|
|
|
|
|
|
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_2;
|
|
|
|
|
|
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
|
|
|
|
|
|
GPIO_InitStructure.Current = GPIO_CURRENT_4mA;
|
|
|
|
|
|
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
|
|
|
|
|
GPIO_InitStructure.SchmittTrigger = DISABLE;
|
|
|
|
|
|
GPIO_InitStructure.Alternate = GPIO0_2_AF_SOUT0;
|
|
|
|
|
|
LHL_GPIO_Init(pGPIO0, &GPIO_InitStructure); // P0.2 -> SOUT0(UART_TX)
|
|
|
|
|
|
|
|
|
|
|
|
/* 2. <20><><EFBFBD><EFBFBD>UART<52><54><EFBFBD><EFBFBD> */
|
|
|
|
|
|
UART_InitStructure.UART_BaudRate = baudrate_bps; // Ӳ<><D3B2><EFBFBD><EFBFBD><EFBFBD>߲<EFBFBD><DFB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>/16
|
|
|
|
|
|
UART_InitStructure.UART_WordLength = UART_WordLength_8b; // <20><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>8
|
|
|
|
|
|
UART_InitStructure.UART_StopBits = UART_StopBits_1; // ֹͣλ<D6B9><CEBB><EFBFBD><EFBFBD>1
|
|
|
|
|
|
UART_InitStructure.UART_Parity = UART_Parity_None; // У<><D0A3>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>
|
|
|
|
|
|
LHL_UART_Init(pUART0, &UART_InitStructure);
|
|
|
|
|
|
//pUART0->IER_DLH = 0x1;
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
UART_IT_EDSSI <EFBFBD><EFBFBD><EFBFBD>ƽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
UART_IT_ELSI <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·״̬<EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
UART_IT_ETBEI <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
UART_IT_ERBFI <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
*/
|
|
|
|
|
|
// LHL_UART_ITConfig( pUART0 ,UART_IT_EDSSI|UART_IT_ELSI|UART_IT_ETBEI|UART_IT_ERBFI , ENABLE);
|
|
|
|
|
|
// NVIC_SetPriority(UART0_IRQn,1);
|
|
|
|
|
|
// NVIC_EnableIRQ(UART0_IRQn);
|
|
|
|
|
|
}
|
|
|
|
|
|
void UART1_Init(uint32_t baudrate_bps)
|
|
|
|
|
|
{
|
|
|
|
|
|
GPIO_InitTypeDef GPIO_InitStructure;
|
|
|
|
|
|
UART_InitTypeDef UART_InitStructure;
|
|
|
|
|
|
|
|
|
|
|
|
/* 1. <20><><EFBFBD><EFBFBD> UART GPIO<49><4F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|
|
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_0;
|
|
|
|
|
|
GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
|
|
|
|
|
|
GPIO_InitStructure.Current = GPIO_CURRENT_4mA;
|
|
|
|
|
|
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
|
|
|
|
|
GPIO_InitStructure.SchmittTrigger = ENABLE;
|
|
|
|
|
|
GPIO_InitStructure.Alternate = GPIO1_0_AF_SIN1;
|
|
|
|
|
|
LHL_GPIO_Init(pGPIO1, &GPIO_InitStructure); // P0.1 -> SIN0(UART_RX)
|
|
|
|
|
|
|
|
|
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_1;
|
|
|
|
|
|
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
|
|
|
|
|
|
GPIO_InitStructure.Current = GPIO_CURRENT_4mA;
|
|
|
|
|
|
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
|
|
|
|
|
GPIO_InitStructure.SchmittTrigger = DISABLE;
|
|
|
|
|
|
GPIO_InitStructure.Alternate = GPIO1_1_AF_SOUT1;
|
|
|
|
|
|
LHL_GPIO_Init(pGPIO1, &GPIO_InitStructure); // P0.2 -> SOUT0(UART_TX)
|
|
|
|
|
|
|
|
|
|
|
|
/* 2. <20><><EFBFBD><EFBFBD>UART<52><54><EFBFBD><EFBFBD> */
|
|
|
|
|
|
UART_InitStructure.UART_BaudRate = baudrate_bps; // Ӳ<><D3B2><EFBFBD><EFBFBD><EFBFBD>߲<EFBFBD><DFB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>/16
|
|
|
|
|
|
UART_InitStructure.UART_WordLength = UART_WordLength_8b; // <20><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>8
|
|
|
|
|
|
UART_InitStructure.UART_StopBits = UART_StopBits_1; // ֹͣλ<D6B9><CEBB><EFBFBD><EFBFBD>1
|
|
|
|
|
|
UART_InitStructure.UART_Parity = UART_Parity_None; // У<><D0A3>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>
|
|
|
|
|
|
LHL_UART_Init(pUART1, &UART_InitStructure);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
UART_IT_EDSSI <EFBFBD><EFBFBD><EFBFBD>ƽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
UART_IT_ELSI <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·״̬<EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
UART_IT_ETBEI <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
UART_IT_ERBFI <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
*/
|
|
|
|
|
|
// LHL_UART_ITConfig( pUART1 ,UART_IT_EDSSI|UART_IT_ELSI|UART_IT_ETBEI|UART_IT_ERBFI , ENABLE);
|
|
|
|
|
|
// NVIC_SetPriority(UART1_IRQn,1);
|
|
|
|
|
|
// NVIC_EnableIRQ(UART1_IRQn);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************************************************************************************/
|
|
|
|
|
|
/*<2A>жϷ<D0B6>ʽ*/
|
|
|
|
|
|
/*********************************************************************************************************************************************/
|
2026-03-20 21:19:04 +08:00
|
|
|
|
/**
|
|
|
|
|
|
* @brief UART0<EFBFBD>жϷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Interrupt Service Routine, ISR<EFBFBD><EFBFBD>
|
|
|
|
|
|
* @note <EFBFBD>˺<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>UART0<EFBFBD>жϴ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>Զ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>
|
|
|
|
|
|
* @warning <EFBFBD>жϴ<EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̣<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ⳤʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
*/
|
2026-03-20 21:16:58 +08:00
|
|
|
|
void UART0_IRQHandler(void)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* <20>շ<EFBFBD><D5B7><EFBFBD><EFBFBD>ݣ<EFBFBD><DDA3><EFBFBD>дRBR_THR_DLL<4C>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
* - <EFBFBD><EFBFBD>ȡʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD>ջ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD>(RBR)<EFBFBD><EFBFBD><EFBFBD>洢UART<EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
* - д<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD>ͱ<EFBFBD><EFBFBD>ּĴ<EFBFBD><EFBFBD><EFBFBD>(THR)<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|
|
|
|
|
// if (LHL_UART_GetFlag(pUART0, UART_FLAG_DR) == SET) // <20>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
// if ((LHL_UART_GetFlag(pUART0, UART_FLAG_THRE) == SET) && \
|
|
|
|
|
|
// (LHL_UART_GetPending(pUART0, UART_IT_ETBEI) == SET)) // <20>жϷ<D0B6><CFB7><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
if (LHL_UART_GetPending(pUART0, UART_IT_RXNE) == SET) // <20>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
{
|
|
|
|
|
|
// uart_buffer[index++] = LHL_UART_ReceiveData(pUART0); // <20><><EFBFBD>뻺<EFBFBD><EBBBBA>
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
if (LHL_UART_GetPending(pUART0, UART_IT_TXE) == SET)
|
|
|
|
|
|
{
|
|
|
|
|
|
// if(index) // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>滹<EFBFBD><E6BBB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
// {
|
|
|
|
|
|
// LHL_UART_SendData(pUART0, uart_buffer[--index]);
|
|
|
|
|
|
// }
|
|
|
|
|
|
// else
|
|
|
|
|
|
// {
|
|
|
|
|
|
// LHL_UART_SendData(pUART0, 0x00); // Send NULL
|
|
|
|
|
|
// LHL_UART_ITConfig(pUART0, UART_IT_ETBEI, DISABLE); // <20>رշ<D8B1><D5B7><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
// }
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
}
|
2026-03-20 21:19:04 +08:00
|
|
|
|
/**
|
|
|
|
|
|
* @brief UART1<EFBFBD>жϷ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Interrupt Service Routine, ISR<EFBFBD><EFBFBD>
|
|
|
|
|
|
* @note <EFBFBD>˺<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>UART1<EFBFBD>жϴ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>Զ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>
|
|
|
|
|
|
* @warning <EFBFBD>жϴ<EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̣<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ⳤʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
*/
|
2026-03-20 21:16:58 +08:00
|
|
|
|
void UART1_IRQHandler(void)
|
|
|
|
|
|
{
|
|
|
|
|
|
if (LHL_UART_GetPending(pUART1, UART_IT_RXNE) == SET) // <20>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
{
|
|
|
|
|
|
// uart_buffer[index++] = LHL_UART_ReceiveData(pUART0); // <20><><EFBFBD>뻺<EFBFBD><EBBBBA>
|
|
|
|
|
|
}
|
|
|
|
|
|
if (LHL_UART_GetPending(pUART1, UART_IT_TXE) == SET)
|
|
|
|
|
|
{
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*********************************************************************************************************************************************/
|
|
|
|
|
|
/*DMA <20><>ʽ*/
|
|
|
|
|
|
/*********************************************************************************************************************************************/
|
2026-03-20 21:19:04 +08:00
|
|
|
|
/*
|
|
|
|
|
|
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD>жϻص<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
<EFBFBD><EFBFBD>DMA_UART_AnyLength_Rx_Init <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD>
|
|
|
|
|
|
|
|
|
|
|
|
*/
|
2026-03-20 21:16:58 +08:00
|
|
|
|
void Btimer_irq_callback(void)
|
|
|
|
|
|
{
|
2026-03-20 21:19:04 +08:00
|
|
|
|
comState.state.ReceivedData = 1 ;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>־λ
|
2026-03-20 21:16:58 +08:00
|
|
|
|
}
|
|
|
|
|
|
//<2F><><EFBFBD><EFBFBD>--------------------------------------------------------------------
|
2026-03-20 21:19:04 +08:00
|
|
|
|
/*
|
|
|
|
|
|
UART DMA<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ճ<EFBFBD>ʼ<EFBFBD><EFBFBD>
|
|
|
|
|
|
DMA_CHANNEL ʹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA<EFBFBD>շ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD>RX TX<EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Btime0ʹ<EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿڶ<EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMAͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ú<EFBFBD> DMA_USE_UART_CHOOSE <EFBFBD>л<EFBFBD>UART0<EFBFBD><EFBFBD><EFBFBD><EFBFBD>UART1<EFBFBD><EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMAͨ<EFBFBD><EFBFBD>
|
|
|
|
|
|
*/
|
2026-03-20 21:16:58 +08:00
|
|
|
|
void DMA_UART_AnyLength_Rx_Init( uint32_t baudrate_bps)
|
|
|
|
|
|
{
|
|
|
|
|
|
DMA_HandleTypeDef DMA_Handle_BTime;
|
|
|
|
|
|
DMA_InitTypeDef DMA_InitStructure[TCD_COUNT]; /* <20><>ɢ<EFBFBD>ۺ<EFBFBD>ģʽ<C4A3>Ķ<EFBFBD><C4B6><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|
|
|
|
|
static DMA_DES_N_TypeDef TCD_Quene[TCD_COUNT] __ALIGN(32);/* DMA TCD<43><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>32λ<32><CEBB><EFBFBD><EFBFBD>*/
|
|
|
|
|
|
static uint8_t BTimerCTRLValue[2]; /* <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD> */
|
|
|
|
|
|
uint16_t IdleFrameValue;
|
|
|
|
|
|
/* 1 <20><><EFBFBD><EFBFBD>DMAUX <20><><EFBFBD><EFBFBD>ԴUART0 RX<52><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MA0 */
|
|
|
|
|
|
DMA_DMAMUX_CFG(DMA_CHANNEL_UART_Rx,REQUEST_SOURCE_UART_RX);//<2F><>DMAMUX<55><58><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD>ͨ<EFBFBD><CDA8>(DMAͨ<41><CDA8>0)
|
|
|
|
|
|
LHL_DMA_Stop(&DMA_Handle_UartRx);
|
2026-03-20 21:19:04 +08:00
|
|
|
|
DMA_Handle_UartRx.Channel = DMA_CHANNEL_UART_Rx; //<2F><><EFBFBD><EFBFBD>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>DMAMUX UART_RX<52><58><EFBFBD><EFBFBD><EFBFBD>ڰ<EFBFBD><DAB0><EFBFBD>UART RX<52><58><EFBFBD><EFBFBD>
|
|
|
|
|
|
DMA_Handle_UartRx.Request = DMA_HARDWARE_REQUEST;
|
|
|
|
|
|
DMA_Handle_UartRx.Mode = DMA_CHAINING_MODE;
|
|
|
|
|
|
DMA_Handle_UartRx.Init.Direction = DMA_PERIPH_TO_MEMORY; // <20><><EFBFBD><EFBFBD>-><3E>ڴ<EFBFBD>
|
|
|
|
|
|
DMA_Handle_UartRx.Init.Src_Address = (uint32_t)(&DMA_UART->RBR_THR_DLL);
|
|
|
|
|
|
DMA_Handle_UartRx.Init.Dest_Address = (uint32_t)comState.RxdData; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
DMA_Handle_UartRx.Init.Data_Width = DMA_DATA_WIDTH_1B;
|
|
|
|
|
|
DMA_Handle_UartRx.Init.Data_Size = 1;
|
|
|
|
|
|
DMA_Handle_UartRx.Init.Repetition = RXD_MAX_DATA;
|
|
|
|
|
|
DMA_Handle_UartRx.Init.Trans_Mode = DMA_SINGLE_TRANSMISSION;
|
|
|
|
|
|
DMA_Handle_UartRx.Init.Chaining = (DMA_CHAINING_t)DMA_CHANNEL_BtimCfg ;//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>дTO_DMA_CHANNEL_x (x=01/2/3/NONE) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>㣬<EFBFBD><E3A3AC><EFBFBD><EFBFBD>ӦDMA_CHANNEL_BtimCfg <20>ı<EFBFBD><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
2026-03-20 21:16:58 +08:00
|
|
|
|
|
|
|
|
|
|
if (LHL_DMA_Init(&DMA_Handle_UartRx) != LHL_OK)
|
|
|
|
|
|
{
|
|
|
|
|
|
while(1);
|
|
|
|
|
|
}
|
|
|
|
|
|
/*1 <20><>ʼ<EFBFBD><CABC>BTIM TImer Base<73><65><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4>ڿ<EFBFBD><DABF><EFBFBD>֡<EFBFBD><D6A1>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ADCʹ<43><CAB9>DMA<4D><41><EFBFBD>в<EFBFBD><D0B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|
|
|
|
|
/*2 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>м<EFBFBD><D0BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱʱ<CAB1><CAB1>ΪIDEL_FRAME_INTERVAL<41><4C><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ */
|
|
|
|
|
|
/*3 <20><><EFBFBD><EFBFBD>BTIMER CTRL<52>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD><EFBFBD>д<EFBFBD><D0B4> */
|
|
|
|
|
|
/*4 <20><><EFBFBD><EFBFBD>BTIM1<4D>жϣ<D0B6><CFA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>ʾ<EFBFBD><CABE><EFBFBD>ڽ<EFBFBD><DABD>յ<EFBFBD>һ֡<D2BB><D6A1><EFBFBD>ݣ<EFBFBD><DDA3>ҿ<EFBFBD><D2BF><EFBFBD>ʱ<EFBFBD>䳬<EFBFBD><E4B3AC><EFBFBD><EFBFBD><EFBFBD>м<EFBFBD><D0BC><EFBFBD><EFBFBD>趨 */
|
|
|
|
|
|
BTimerCTRLValue[0] = 0;
|
|
|
|
|
|
BTimerCTRLValue[1] = BTIM_TCTRL_TEN_Msk | BTIM_TCTRL_TIE_Msk;
|
|
|
|
|
|
|
|
|
|
|
|
IdleFrameValue = (uint16_t)(SystemCoreClock * IDLE_FRAME_INTERVAL / baudrate_bps) - 1;
|
|
|
|
|
|
BTIM0_Init(IdleFrameValue);
|
|
|
|
|
|
Btimer_register_irq_callback(BTIMER_0,Btimer_irq_callback); //ע<><D7A2><EFBFBD>жϺ<D0B6><CFBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡<EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
|
|
|
|
|
|
DMA_Handle_BTime.Channel = DMA_CHANNEL_BtimCfg; //<2F><><EFBFBD><EFBFBD>DMAͨ<41><CDA8>1<EFBFBD><31><EFBFBD><EFBFBD>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڰ<EFBFBD><DAB0><EFBFBD>BTIM<49><4D><EFBFBD>ò<EFBFBD><C3B2><EFBFBD>
|
|
|
|
|
|
DMA_Handle_BTime.Request = DMA_HARDWARE_REQUEST;
|
|
|
|
|
|
DMA_Handle_BTime.Mode = DMA_SCATTER_GATHER_MODE; // <20><>ɢ-<2D>ۺ<EFBFBD>ģʽ
|
|
|
|
|
|
DMA_Handle_BTime.TCD_Count = TCD_COUNT; // TCD<43><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
DMA_Handle_BTime.TCD_List = TCD_Quene; // TCD<43><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
DMA_Handle_BTime.TCD_Init = DMA_InitStructure; // TCD<43><44>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
|
|
|
|
|
|
DMA_InitStructure[0].Direction = DMA_MEMORY_TO_PERIPH; // TCD0<44><30><EFBFBD>ڸ<EFBFBD>λBTIM<49>Ĵ<EFBFBD><C4B4><EFBFBD>
|
|
|
|
|
|
DMA_InitStructure[0].Src_Address = (uint32_t)&BTimerCTRLValue[0];
|
|
|
|
|
|
DMA_InitStructure[0].Dest_Address = (uint32_t)(&BTIM->TCTRL_0);
|
|
|
|
|
|
DMA_InitStructure[0].Data_Width = DMA_DATA_WIDTH_1B;
|
|
|
|
|
|
DMA_InitStructure[0].Data_Size = 1;
|
|
|
|
|
|
DMA_InitStructure[0].Repetition = 1;
|
|
|
|
|
|
DMA_InitStructure[0].Trans_Mode = DMA_CYCLIC_TRANSMISSION;
|
|
|
|
|
|
DMA_InitStructure[0].TCD_Address = (int32_t)&TCD_Quene[1];
|
|
|
|
|
|
DMA_InitStructure[0].Auto_Start = DISABLE;
|
|
|
|
|
|
DMA_InitStructure[0].INT_Major = DISABLE;
|
|
|
|
|
|
DMA_InitStructure[0].INT_Half = DISABLE;
|
|
|
|
|
|
DMA_InitStructure[0].Chaining = TO_DMA_CHANNEL_NONE;
|
|
|
|
|
|
|
|
|
|
|
|
DMA_InitStructure[1].Direction = DMA_MEMORY_TO_PERIPH; // TCD1<44><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>BTIM<49>Ĵ<EFBFBD><C4B4><EFBFBD>
|
|
|
|
|
|
DMA_InitStructure[1].Src_Address = (uint32_t)&BTimerCTRLValue[1];
|
|
|
|
|
|
DMA_InitStructure[1].Dest_Address = (uint32_t)(&BTIM->TCTRL_0);
|
|
|
|
|
|
DMA_InitStructure[1].Data_Width = DMA_DATA_WIDTH_1B;
|
|
|
|
|
|
DMA_InitStructure[1].Data_Size = 1;
|
|
|
|
|
|
DMA_InitStructure[1].Repetition = 1;
|
|
|
|
|
|
DMA_InitStructure[1].Trans_Mode = DMA_CYCLIC_TRANSMISSION;
|
|
|
|
|
|
DMA_InitStructure[1].TCD_Address = (int32_t)&TCD_Quene[0];
|
|
|
|
|
|
DMA_InitStructure[1].Auto_Start = ENABLE;
|
|
|
|
|
|
DMA_InitStructure[1].INT_Major = DISABLE;
|
|
|
|
|
|
DMA_InitStructure[1].INT_Half = DISABLE;
|
|
|
|
|
|
DMA_InitStructure[1].Chaining = TO_DMA_CHANNEL_NONE;
|
|
|
|
|
|
if (LHL_DMA_Init(&DMA_Handle_BTime) != LHL_OK)
|
|
|
|
|
|
{
|
|
|
|
|
|
while(1);
|
|
|
|
|
|
}
|
|
|
|
|
|
/*DMA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>*/
|
|
|
|
|
|
LHL_DMA_Start(&DMA_Handle_UartRx); /* <20><>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DMA0 ,<2C><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>*/
|
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
2026-03-20 21:19:04 +08:00
|
|
|
|
//<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD>ʳ<EFBFBD><CAB3><EFBFBD>
|
2026-03-20 21:16:58 +08:00
|
|
|
|
void Get_UART_Rx_ActualLength(void)
|
|
|
|
|
|
{
|
|
|
|
|
|
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݳ<EFBFBD><DDB3>ȼ<EFBFBD><C8BC><EFBFBD>,<2C><>ȡ<EFBFBD><C8A1>ǰ֡<C7B0><D6A1><EFBFBD><EFBFBD>*/
|
|
|
|
|
|
comState.RxLenth = LHL_DMA_GetDestAddress(DMA_CHANNEL_UART_Rx) - (u32)&comState.RxdData ;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
//<2F><><EFBFBD><EFBFBD>--------------------------------------------------------------------
|
|
|
|
|
|
void DMA_UART_Tx_Init(void)
|
|
|
|
|
|
{
|
|
|
|
|
|
DMA_DMAMUX_CFG(DMA_CHANNEL_UART_Tx,REQUEST_SOURCE_UART_TX);//<2F><>DMAMUX<55><58><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD>ͨ<EFBFBD><CDA8>(DMAͨ<41><CDA8>0)
|
|
|
|
|
|
|
|
|
|
|
|
/* 3.4 <20><><EFBFBD><EFBFBD>DMAͨ<41><CDA8>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><F0BBBAB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD><DDB0>˵<EFBFBD>UART0 TX<54><58><EFBFBD><EFBFBD> */
|
|
|
|
|
|
DMA_Handle_UartTx.Channel = DMA_CHANNEL_UART_Tx;
|
|
|
|
|
|
DMA_Handle_UartTx.Mode = DMA_DIRECT_MODE;
|
|
|
|
|
|
DMA_Handle_UartTx.Request = DMA_HARDWARE_REQUEST;
|
|
|
|
|
|
DMA_Handle_UartTx.Init.Direction = DMA_MEMORY_TO_PERIPH; // <20>ڴ<EFBFBD>-><3E><><EFBFBD><EFBFBD>
|
|
|
|
|
|
DMA_Handle_UartTx.Init.Src_Address = (uint32_t)&comState.TxdData; // Դ<><D4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|
|
|
|
|
DMA_Handle_UartTx.Init.Dest_Address = (uint32_t)(&DMA_UART->RBR_THR_DLL); // Ŀ<>ģ<EFBFBD>UART TX<54>Ĵ<EFBFBD><C4B4><EFBFBD>
|
|
|
|
|
|
DMA_Handle_UartTx.Init.Data_Width = DMA_DATA_WIDTH_1B;
|
|
|
|
|
|
DMA_Handle_UartTx.Init.Data_Size = 1;
|
|
|
|
|
|
DMA_Handle_UartTx.Init.Repetition = comState.TxLenth ;
|
|
|
|
|
|
DMA_Handle_UartTx.Init.Trans_Mode = DMA_SINGLE_TRANSMISSION; // <20><><EFBFBD><EFBFBD>ģʽ
|
|
|
|
|
|
if (LHL_DMA_Init(&DMA_Handle_UartTx) != LHL_OK)
|
|
|
|
|
|
{
|
|
|
|
|
|
while(1); // DMA Init Error
|
|
|
|
|
|
}
|
|
|
|
|
|
// /* ʹ<><CAB9>DMA<4D>ж<EFBFBD> */
|
|
|
|
|
|
LHL_DMA_ITConfig(&DMA_Handle_UartTx, DMA_IT_MAJOR, ENABLE); // <20><><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD>ж<EFBFBD>
|
|
|
|
|
|
// NVIC_EnableIRQ(DMA1_CH0_IRQn); //DMA_CHANNEL_UART_Tx
|
|
|
|
|
|
|
|
|
|
|
|
LHL_DMA_Start(&DMA_Handle_UartTx); /* <20><>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DMA0 ,<2C><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>*/
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|