Temp/CHJ
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

差异

Browse Source
This commit is contained in:
guishenking
2026-03-20 21:19:53 +08:00
parent 9d3b4b836f
commit 6a749331db
125 changed files with 29972 additions and 23051 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
library/inc/lh32m0g3x_xlink.h
View File

@@ -28,16 +28,16 @@ typedef enum
XLINK0_INPUT_XB_IN1,
XLINK0_INPUT_XB_IN2,
XLINK0_INPUT_XB_IN3,
XLINK0_INPUT_TIM0_TRGO,
XLINK0_INPUT_TIM0_INT,
XLINK0_INPUT_TIM1_TRGO,
XLINK0_INPUT_TIM1_INT,
XLINK0_INPUT_TIM2_TRGO,
XLINK0_INPUT_TIM2_INT,
XLINK0_INPUT_ADC0_CNV_DONE,
XLINK0_INPUT_ADC1_CNV_DONE,
XLINK0_INPUT_LPTIM0_INT = 0x10u,
XLINK0_INPUT_LPTIM1_INT,
XLINK0_INPUT_BTIM0_TRIGGER,
XLINK0_INPUT_LPTIM1_INT = 0x10u,
XLINK0_INPUT_LPTIM2_INT,
XLINK0_INPUT_BTIM1_TRIGGER,
XLINK0_INPUT_BTIM2_TRIGGER,
XLINK0_INPUT_RTC_ALARM,
XLINK0_INPUT_FAULT,
XLINK0_INPUT_SOFT_SYNC,
@@ -55,20 +55,20 @@ typedef enum
typedef enum
{
XLINK1_INPUT_TIM0_TRGO = 0x00u, /*!< Cross Link 1 输入源 */
XLINK1_INPUT_TIM0_INT,
XLINK1_INPUT_TIM1_TRGO,
XLINK1_INPUT_TIM1_TRGO = 0x00u, /*!< Cross Link 1 输入源 */
XLINK1_INPUT_TIM1_INT,
XLINK1_INPUT_TIM2_TRGO,
XLINK1_INPUT_TIM2_INT,
XLINK1_INPUT_ADC0_CNV_DONE,
XLINK1_INPUT_ADC1_CNV_DONE,
XLINK1_INPUT_XB_IN0,
XLINK1_INPUT_XB_IN1,
XLINK1_INPUT_XB_IN2,
XLINK1_INPUT_XB_IN3,
XLINK1_INPUT_LPTIM0_INT = 0x0Eu,
XLINK1_INPUT_LPTIM1_INT,
XLINK1_INPUT_BTIM0_TRIGGER,
XLINK1_INPUT_LPTIM1_INT = 0x0Eu,
XLINK1_INPUT_LPTIM2_INT,
XLINK1_INPUT_BTIM1_TRIGGER,
XLINK1_INPUT_BTIM2_TRIGGER,
XLINK1_INPUT_RTC_ALARM,
XLINK1_INPUT_FAULT,
XLINK1_INPUT_SOFT_SYNC,
@@ -89,12 +89,12 @@ typedef enum
XLINK0_OUTPUT_ADC0_TRIG = 0x0008U,
XLINK0_OUTPUT_ADC1_TRIG = 0x0808U,
XLINK0_OUTPUT_DAC_SYNC = 0x1008U,
XLINK0_OUTPUT_TIM0_ITR0 = 0x1808U,
XLINK0_OUTPUT_TIM1_ITR0 = 0x000CU,
XLINK0_OUTPUT_TIM1_ITR0 = 0x1808U,
XLINK0_OUTPUT_TIM2_ITR0 = 0x000CU,
XLINK0_OUTPUT_MIO_TRIGGER_IN0 = 0x080CU,
XLINK0_OUTPUT_MIO_TRIGGER_IN1 = 0x100CU,
XLINK0_OUTPUT_LPTIM0_CL = 0x180CU,
XLINK0_OUTPUT_LPTIM1_CL = 0x0010U,
XLINK0_OUTPUT_LPTIM1_CL = 0x180CU,
XLINK0_OUTPUT_LPTIM2_CL = 0x0010U,
} XLINK0_OUTPUT_PORT_t;
/**