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guishenking
2026-03-20 21:19:53 +08:00
parent 9d3b4b836f
commit 6a749331db
125 changed files with 29972 additions and 23051 deletions
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395
user/MCU/lhl_adc_dma.c Normal file
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#include "../main/SystemInclude.h"
/*********************************************************************************************************************************************/
/*DMA <20>жϷ<D0B6>ʽ */
/*********************************************************************************************************************************************/
DMA_HandleTypeDef DMA_Handle_ADC0,DMA_Handle_ADC1;
/**------------------------------------------------------------------------
* @brief <20><>ʼ<EFBFBD><CABC>ADC<44><43>DMA<4D><41><EFBFBD>䣨<EFBFBD><E4A3A8>ͨ<EFBFBD><CDA8>ѭ<EFBFBD><D1AD>ģʽ<C4A3><CABD>
* @note <20><><EFBFBD><EFBFBD>DMA<4D><41>ADCת<43><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD>˵<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD>ڴ滺<DAB4><E6BBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>ѭ<EFBFBD><D1AD>ģʽ<C4A3><CABD>
* <20><>ʹ<EFBFBD><CAB9>DMA<4D><41><EFBFBD>жϡ<D0B6><CFA1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param ADCx: ADCʵ<43><CAB5> (ADC_0 / ADC_1)
* @param dest_addr: Ŀ<><C4BF><EFBFBD>ڴ滺<DAB4><E6BBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD>豣<EFBFBD><E8B1A3><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7>
* @param dest_count: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȣ<EFBFBD><C8A3><EFBFBD><EFBFBD>ظ<EFBFBD><D8B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD>ģʽ<C4A3><CABD>ÿ<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD>
* @example DMA_ADC_Init(ADC_0, (u32*)adc_buffer, 32);
**/
void DMA_ADC_Init(ADC_ID_t ADCx ,u32 *dest_addr , u8 dest_count)
{
DMA_HandleTypeDef DMA_Handle_ADC;
//DMA_Handle_ADC.Channel = DMA_CHANNEL_ADC0;
DMA_Handle_ADC.Mode = DMA_DIRECT_MODE; // ֱ<><D6B1> Mode
DMA_Handle_ADC.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADC.Init.Direction = DMA_PERIPH_TO_MEMORY; // <20><><EFBFBD><EFBFBD>-><3E>ڴ<EFBFBD>
//DMA_Handle_ADC.Init.Src_Address = (uint32_t)&(MainADC->ADC_DATA_0);
DMA_Handle_ADC.Init.Dest_Address = (uint32_t)dest_addr;
DMA_Handle_ADC.Init.Data_Width = DMA_DATA_WIDTH_4B;
DMA_Handle_ADC.Init.Data_Size = 1;
DMA_Handle_ADC.Init.Repetition = dest_count;
DMA_Handle_ADC.Init.Trans_Mode = DMA_CYCLIC_TRANSMISSION; // ѭ<><D1AD>ģʽ
if(ADCx == ADC_0)
{
//<2F><><EFBFBD>ӵ<EFBFBD>DMA
LHL_ADC_DMACmd(ADC_0, ENABLE);
DMA_DMAMUX_CFG(DMA_CHANNEL_ADC_0 ,REQUEST_SOURCE_ADC0);
DMA_Handle_ADC0 = DMA_Handle_ADC;
DMA_Handle_ADC0.Channel = DMA_CHANNEL_ADC_0;
DMA_Handle_ADC0.Init.Src_Address = (uint32_t)&(MainADC->ADC_DATA_0);
if (LHL_DMA_Init(&DMA_Handle_ADC0) != LHL_OK)
{
while(1);
}
LHL_DMA_ITConfig(&DMA_Handle_ADC0, DMA_IT_MAJOR, ENABLE);// <20><><EFBFBD>ж<EFBFBD>
// LHL_DMA_Start(&DMA_Handle_ADC0);
}
else if(ADCx == ADC_1)
{
//<2F><><EFBFBD>ӵ<EFBFBD>DMA
LHL_ADC_DMACmd(ADC_1, ENABLE);
DMA_DMAMUX_CFG(DMA_CHANNEL_ADC_1 ,REQUEST_SOURCE_ADC1);
DMA_Handle_ADC1 = DMA_Handle_ADC;
DMA_Handle_ADC1.Channel = DMA_CHANNEL_ADC_1;
DMA_Handle_ADC1.Init.Src_Address = (uint32_t)&(MainADC->ADC_DATA_1);
if (LHL_DMA_Init(&DMA_Handle_ADC1) != LHL_OK)
{
while(1);
}
LHL_DMA_ITConfig(&DMA_Handle_ADC1, DMA_IT_MAJOR, ENABLE);// <20><><EFBFBD>ж<EFBFBD>
// LHL_DMA_Start(&DMA_Handle_ADC1);
}
}
/**------------------------------------------------------------------------
* @brief <20><><EFBFBD><EFBFBD>ADC<44><43>DMA<4D><41><EFBFBD><EFBFBD>
* @note <20><><EFBFBD><EFBFBD>DMAͨ<41><CDA8><EFBFBD><EFBFBD>ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD>ADCת<43><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
* @param ADCx: ADCʵ<43><CAB5> (ADC_0 / ADC_1)
* @example DMA_StartADC(ADC_0);
**/
void DMA_StartADC(ADC_ID_t ADCx)
{
if(ADCx == ADC_0) { LHL_DMA_Start(&DMA_Handle_ADC0); LHL_ADC_Start(ADC_0); }
else { LHL_DMA_Start(&DMA_Handle_ADC1); LHL_ADC_Start(ADC_1); }
}
/**------------------------------------------------------------------------
* @brief ֹͣADC<44><43>DMA<4D><41><EFBFBD><EFBFBD>
* @param ADCx: ADCʵ<43><CAB5> (ADC_0 / ADC_1)
* @example DMA_StopADC(ADC_0);
**/
void DMA_StopADC(ADC_ID_t ADCx)
{
if(ADCx == ADC_0) { LHL_DMA_Stop(&DMA_Handle_ADC0); LHL_ADC_Stop(ADC_0); }
else { LHL_DMA_Stop(&DMA_Handle_ADC1); LHL_ADC_Stop(ADC_1); }
}
/*********************************************************************************************************************************************/
/*DMA <20><><EFBFBD>з<EFBFBD>ʽ */
/*********************************************************************************************************************************************/
/* <20><><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<43><30><EFBFBD><EFBFBD>
* ==<3D><>ADCת<43><D7AA><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>DMA0<41><30><EFBFBD><EFBFBD>ADC0<43><30><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>
* ==<3D><>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<43><30><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>ת<EFBFBD><D7AA>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>
* ==<3D><>DMA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD>ADC0<43><30>һ<EFBFBD><D2BB>ͨ<EFBFBD><CDA8><EFBFBD>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>
* ==<3D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCͨ<43><CDA8>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹͣ<CDA3><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD>ж<EFBFBD> */
//DMA_ADC<44><43><EFBFBD>з<EFBFBD>ʽ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD>ȡ=========================================================================
DMA_HandleTypeDef DMA_Handle_ADCstatus ,DMA_Handle_ADCcontrol;
//ADC_Data_t adcBuffer[8]; /* <20><>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
/**------------------------------------------------------------------------
* @brief <20><>ʼ<EFBFBD><CABC>ADC0<43><30>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMAģʽ
* @note <20><><EFBFBD><EFBFBD>ADC0<43><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD>Զ<EFBFBD><D4B6>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>˫DMAЭ<41><D0AD><EFBFBD><EFBFBD>
* - DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD>ݣ<EFBFBD>
* - DMA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCͨ<43><CDA8><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD><EFBFBD><EFBFBD>
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>贫<EFBFBD><E8B4AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ýṹ<C3BD>壬<EFBFBD><E5A3AC><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD>б<EFBFBD><D0B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʡ<EFBFBD><CAA1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȳ<EFBFBD><C8B2><EFBFBD><EFBFBD><EFBFBD>
* @param seq_config: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ýṹ<C3BD><E1B9B9>ָ<EFBFBD>룬<EFBFBD><EBA3AC><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʡ<EFBFBD><CAA1><EFBFBD><EFBFBD>桢<EFBFBD><E6A1A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @example DMA_ADC0_SingleChannel_SEQ_Init(&my_seq_config);
**/
void DMA_ADC0_SingleChannel_SEQ_Init(__SeqConfig_TypeDef* seq_config)
{
ADC_InitTypeDef ADC_InitStructure;
ADC_SingleCSInitTypeDef ADC_CSInitStructure; /* <20><>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD>ṹ<EFBFBD><E1B9B9> */
ADC_Config_t ADC_Config[seq_config->SeqCount] __ALIGN(32); /* <20><>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>32λ<32><CEBB><EFBFBD><EFBFBD> */
DMAMUX_InitTypeDef DMAMUX_InitStructure;
/* 1. <20><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼ */
ADC_REF_Init(REF_INTERNAL_2P5V,REF_INTERNAL_2P5V);
/* 2.1 <20><>ʼ<EFBFBD><CABC>ADC0<43><30>ADC1ͨ<31><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCͨ<43>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̶<EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>
* Ȼ<><C8BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽר<CABD>ýṹ<C3BD><E1B9B9><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD>˳<EFBFBD><CBB3>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ */
ADC_InitStructure.FS = seq_config->SPS;// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>12.5SPS<EFBFBD><EFBFBD>4ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѯ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><EFBFBD><EFBFBD>1SPS<EFBFBD><EFBFBD>
ADC_InitStructure.PGA = seq_config->Gain;
ADC_InitStructure.Code = ADC_CODE_BIPOLAR;
ADC_InitStructure.ReferenceSelect = ADC_REF_REFP_to_REFN;
ADC_InitStructure.REF_BUFP = ENABLE;
ADC_InitStructure.REF_BUFM = ENABLE;
ADC_InitStructure.REF_Precharge = DISABLE;
ADC_InitStructure.Reference = 2500.0f;
ADC_CSInitStructure.ADC_ID = ADC_0; // ADC0
ADC_CSInitStructure.ADC_CFG = ADC_Config; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_CSInitStructure.Active_Channels = seq_config->SeqCount; // <20><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_CSInitStructure.Cycle_Mode = DISABLE; // ѭ<><D1AD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD><D0BA>ȴ<EFBFBD><C8B4>´δ<C2B4><CEB4><EFBFBD><EFBFBD><EFBFBD>
ADC_CSInitStructure.Sequencer_Trigger = ADC_TRIGGER_SOFTWARE; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>ֹͣ<CDA3><D6B9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD>βɼ<CEB2>һ<EFBFBD><D2BB>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>
for (int i = 0; i < seq_config->SeqCount; i++) { //SeqCount =4: ADC0<43><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>0->1->2->3->0->1->...
ADC_CSInitStructure.AINP_Channel[i] = seq_config->SeqChannel[i].ainp_channel;
ADC_CSInitStructure.AINM_Channel[i] = seq_config->SeqChannel[i].ainm_channel;
}
LHL_ADC_SingleChannelSequencerInit(&ADC_InitStructure, &ADC_CSInitStructure);
/* 2.2 ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD>ӦADC<44><43>DMA<4D><41><EFBFBD><EFBFBD> */
LHL_ADC_DMACmd(ADC_0, ENABLE); // ʹ<><CAB9>ADC0<43><30>DMA<4D><41><EFBFBD><EFBFBD>
/* 3.1 <20><><EFBFBD><EFBFBD>DMAUX<55><58>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>ADC0 */
DMA_DMAMUX_CFG(DMA_CHANNEL_ADC_STA ,REQUEST_SOURCE_ADC0);
/* 3.2 <20><><EFBFBD><EFBFBD>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD>ڶ<EFBFBD>ȡADC0<43><30><EFBFBD>ݺ<EFBFBD>״̬ */
DMA_Handle_ADCstatus.Channel = DMA_CHANNEL_ADC_STA;
DMA_Handle_ADCstatus.Mode = DMA_CHAINING_MODE;
DMA_Handle_ADCstatus.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADCstatus.Init.Direction = DMA_PERIPH_TO_MEMORY;
DMA_Handle_ADCstatus.Init.Src_Address = (uint32_t)(&MainADC->ADC_STATUS_0); // Դ<><D4B4>ַ<EFBFBD><D6B7>ȡADC0<43><30><EFBFBD><EFBFBD>
DMA_Handle_ADCstatus.Init.Dest_Address = (uint32_t)seq_config->adcBuffer;
DMA_Handle_ADCstatus.Init.Data_Width = DMA_DATA_WIDTH_4B;
DMA_Handle_ADCstatus.Init.Data_Size = 2; // ״̬<D7B4><CCAC><EFBFBD><EFBFBD><EFBFBD>ݹ<EFBFBD>2<EFBFBD><32><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
DMA_Handle_ADCstatus.Init.Repetition = seq_config->SeqCount;
DMA_Handle_ADCstatus.Init.Trans_Mode = DMA_CYCLIC_TRANSMISSION;
DMA_Handle_ADCstatus.Init.Chaining = (DMA_CHAINING_t)DMA_CHANNEL_ADC_CTL; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD> TO_DMA_CHANNEL_3 // <20><><EFBFBD>ɺ<EFBFBD><C9BA>Զ<EFBFBD><D4B6><EFBFBD><EFBFBD><EFBFBD>DMA1
if (LHL_DMA_Init(&DMA_Handle_ADCstatus) != LHL_OK)
{
while(1); // DMA Init Error
}
/* 4.1 <20><><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<43><30>ͨ<EFBFBD><CDA8><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> */
DMA_Handle_ADCcontrol.Channel = DMA_CHANNEL_ADC_CTL; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>->hDMA1
DMA_Handle_ADCcontrol.Mode = DMA_DIRECT_MODE;
DMA_Handle_ADCcontrol.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADCcontrol.Init.Direction = DMA_MEMORY_TO_PERIPH;
DMA_Handle_ADCcontrol.Init.Src_Address = (uint32_t)ADC_Config; // Դ<><D4B4>ַ<EFBFBD><D6B7>ȡADC0ͨ<30><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD>
DMA_Handle_ADCcontrol.Init.Dest_Address = (uint32_t)(&pADC->ADC_CONTROL_0); // Ŀ<>ĵ<EFBFBD>ַ<EFBFBD><D6B7>ADC0<43>Ĵ<EFBFBD><C4B4><EFBFBD>
DMA_Handle_ADCcontrol.Init.Data_Width = DMA_DATA_WIDTH_4B;
DMA_Handle_ADCcontrol.Init.Data_Size = 2;
DMA_Handle_ADCcontrol.Init.Repetition = seq_config->SeqCount;
DMA_Handle_ADCcontrol.Init.Trans_Mode = DMA_CYCLIC_TRANSMISSION;
if (LHL_DMA_Init(&DMA_Handle_ADCcontrol) != LHL_OK)
{
while(1); // DMA Init Error
}
/* 4.2 ʹ<><CAB9>DMA<4D>ж<EFBFBD> */
LHL_DMA_ITConfig(&DMA_Handle_ADCcontrol, DMA_IT_MAJOR, ENABLE);
// NVIC_EnableIRQ(DMA1_CH1_IRQn); //ADCcontrol<6F><6C><EFBFBD>ж<EFBFBD>
// /* 5. <20><>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DMA*/
// LHL_DMA_Start(&DMA_Handle_ADCstatus);
// memset(&(adcBuffer),0,sizeof(adcBuffer));
}
/**------------------------------------------------------------------------
* @brief <20><><EFBFBD><EFBFBD>ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD>
* @note <20><><EFBFBD><EFBFBD>DMA0<41><30>״̬<D7B4><CCAC><EFBFBD>ˣ<EFBFBD><CBA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCת<43><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6>ֻ<EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>
* @param ADCx: ADCʵ<43><CAB5> (<28><>֧<EFBFBD><D6A7>ADC_0<5F><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><DAB2>ѹ̶<D1B9>ΪADC0)
* @example StartDMA_SEQ_ADC(ADC_0);
**/
void StartDMA_SEQ_ADC(ADC_ID_t ADCx)
{
if(ADCx == ADC_0) { LHL_DMA_Start(&DMA_Handle_ADCstatus); LHL_ADC_Start(ADC_0); }
else { LHL_DMA_Start(&DMA_Handle_ADCstatus); LHL_ADC_Start(ADC_1); }
}
/**------------------------------------------------------------------------
* @brief ֹͣADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD>
* @param ADCx: ADCʵ<43><CAB5> (ADC_0 / ADC_1)
* @note ֹͣDMAͨ<41><CDA8><EFBFBD><EFBFBD>ֹͣADCת<43><D7AA><EFBFBD><EFBFBD>
* @example StopDMA_SEQ_ADC(ADC_0);
**/
void StopDMA_SEQ_ADC(ADC_ID_t ADCx)
{
if(ADCx == ADC_0) { LHL_DMA_Stop(&DMA_Handle_ADC0); LHL_ADC_Stop(ADC_0); }
else { LHL_DMA_Stop(&DMA_Handle_ADC1); LHL_ADC_Stop(ADC_1); }
}
//============================================================
#if 0
/* <20><><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><DFBC><EFBFBD> <20><><EFBFBD><EFBFBD>ADC0<43><30><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC>ģʽ<C4A3><CABD>ADC1ͬʱ<CDAC><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* ==<3D><>ADCת<43><D7AA><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>DMA0<41><30><EFBFBD><EFBFBD>ADC0<43><30>ADC1<43><31><EFBFBD><EFBFBD><EFBFBD>ݡ<EFBFBD>
* ==<3D><>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD><EFBFBD>ADC0<43><30>ADC1<43><31><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>ADCת<43><D7AA>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
typedef struct{ /* ˫ADC<44><43>˫<EFBFBD><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
ADC_DualData_t BufferA[SEQUENCER_COUNT];
ADC_DualData_t BufferB[SEQUENCER_COUNT];
} ADC_DualData_Buffer_t;
ADC_DualData_Buffer_t adcDualBuffer; /* ˫ADC<44><43><EFBFBD><EFBFBD><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD> */
#define TCD_COUNT 2 /* ˫<><CBAB><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
void DMA_ADC0_1_DualChannel_Init(void)
{
ADC_InitTypeDef ADC_InitStructure;
ADC_DualCSInitTypeDef ADC_DualCSInitStructure; /* ˫ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD>ṹ<EFBFBD><E1B9B9> */
ADC_DualConfig_t ADC_DualConfig[SEQUENCER_COUNT] __ALIGN(128); /* ˫ADC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>128λ<38><CEBB><EFBFBD><EFBFBD> */
DMAMUX_InitTypeDef DMAMUX_InitStructure;
DMA_HandleTypeDef DMA_Handle_ADCstatus ,DMA_Handle_ADCcontrol;/* <20><><EFBFBD>õ<EFBFBD>2·DMA */
DMA_InitTypeDef DMA_InitStructure[TCD_COUNT]; /* TCD<43><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9> */
DMA_DES_N_TypeDef TCD_Quene[TCD_COUNT] __ALIGN(32); /* DMA TCD<43><44><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>32λ<32><CEBB><EFBFBD><EFBFBD>*/
/* 1.1 <20><>ʼ<EFBFBD><CABC><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD>׼ */
ADC_REF_Init(REF_INTERNAL_2P5V,REF_INTERNAL_OFF);
/* 1.2 <20><>ʼ<EFBFBD><CABC>ADC0<43><30>ADC1ͨ<31><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADCͨ<43>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>
* Ȼ<><C8BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽר<CABD>ýṹ<C3BD><E1B9B9><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD>ţ<EFBFBD><C5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD>ģʽ<C4A3><CABD><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ */
ADC_InitStructure.FS = SPS_12P5; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_InitStructure.PGA = GAIN1;
ADC_InitStructure.Code = ADC_CODE_BIPOLAR;
ADC_InitStructure.ReferenceSelect = ADC_REF_REFP_to_REFN;
ADC_InitStructure.REF_BUFP = ENABLE;
ADC_InitStructure.REF_BUFM = ENABLE;
ADC_InitStructure.REF_Precharge = DISABLE;
ADC_InitStructure.Reference = 2500.0f;
ADC_DualCSInitStructure.ADC_CFGs = ADC_DualConfig; // ˫ͨ<CBAB><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
ADC_DualCSInitStructure.Active_Channels = SEQUENCER_COUNT; // <20><><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>4<EFBFBD><34>
ADC_DualCSInitStructure.Cycle_Mode = DISABLE; // ѭ<><D1AD>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD><D0BA>ȴ<EFBFBD><C8B4>´δ<C2B4><CEB4><EFBFBD><EFBFBD><EFBFBD>
ADC_DualCSInitStructure.Sequencer_Trigger = ADC_TRIGGER_SOFTWARE; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD>к<EFBFBD>ֹͣ<CDA3><D6B9>Ӳ<EFBFBD><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD>βɼ<CEB2>һ<EFBFBD><D2BB>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>
for (int i = 0; i < SEQUENCER_COUNT; i++) {
ADC_DualCSInitStructure.AINP0_Channel[i] = ADC0seq_configs[i].ainp_channel;
ADC_DualCSInitStructure.AINM0_Channel[i] = ADC0seq_configs[i].ainm_channel;
ADC_DualCSInitStructure.AINP1_Channel[i] = ADC1seq_configs[i].ainp_channel;
ADC_DualCSInitStructure.AINM1_Channel[i] = ADC1seq_configs[i].ainm_channel;
}
LHL_ADC_DualChannelSequencerInit(&ADC_InitStructure, &ADC_DualCSInitStructure); // <20><>ʼ<EFBFBD><CABC>ADC˫<43><CBAB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
/* 1.3 ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>ͬ<EFBFBD><CDAC>ģʽ<C4A3><CABD><EFBFBD><EFBFBD>ӦADC<44><43>DMA<4D><41><EFBFBD><EFBFBD> */
LHL_ADC_SetSync(ENABLE); // <20><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>ͬ<EFBFBD><CDAC>ģʽ
LHL_ADC_DMACmd(ADC_0, ENABLE); // <20><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>ADC0<43><30>ADC1<43><31>DMA<4D><41><EFBFBD><EFBFBD>
LHL_ADC_DMACmd(ADC_1, ENABLE);
/* 2. <20><><EFBFBD><EFBFBD>DMAUX<55><58>DMA0<41><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>ADC0 */
DMA_DMAMUX_CFG(DMA_CHANNEL_0 ,REQUEST_SOURCE_ADC0);
/* 3. <20><><EFBFBD><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD>ڶ<EFBFBD>ȡADC0<43><30>ADC1<43><31><EFBFBD><EFBFBD><EFBFBD>ݺ<EFBFBD>״̬ */
DMA_Handle_ADCstatus.Channel = DMA_CHANNEL_0; // <20><><EFBFBD><EFBFBD>hDMA0
DMA_Handle_ADCstatus.Mode = DMA_SCATTER_GATHER_MODE; // <20><>ɢ<EFBFBD>ۺ<EFBFBD>ģʽ
DMA_Handle_ADCstatus.Request = DMA_HARDWARE_REQUEST; // Ӳ<><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DMA_Handle_ADCstatus.TCD_Count = TCD_COUNT; // 2<><32>TCD<43><44><EFBFBD><EFBFBD>˫<EFBFBD><CBAB><EFBFBD><EFBFBD>
DMA_Handle_ADCstatus.TCD_List = TCD_Quene; // TCD<43><44><EFBFBD><EFBFBD>
DMA_Handle_ADCstatus.TCD_Init = DMA_InitStructure; // TCD<43><44>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
DMA_InitStructure[0].Direction = DMA_PERIPH_TO_MEMORY; // TCD0<44><30><EFBFBD><EFBFBD>ADC0<43><30>ADC1<43><31><EFBFBD><EFBFBD><EFBFBD>ݶ<EFBFBD>ȡ
DMA_InitStructure[0].Src_Address = (uint32_t)(&pADC->IO_CONTROL_IOUT);
DMA_InitStructure[0].Data_Width = DMA_DATA_WIDTH_16B;
DMA_InitStructure[0].Dest_Address = (uint32_t)&adcDualBuffer.BufferA[0];// ָ<>򻺴<EFBFBD><F2BBBAB4><EFBFBD>A
DMA_InitStructure[0].Data_Size = 2;
DMA_InitStructure[0].Repetition = SEQUENCER_COUNT;
DMA_InitStructure[0].Trans_Mode = DMA_INTERVAL_TRANSMISSION; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڶ<EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڵļĴ<C4BC><C4B4><EFBFBD>
DMA_InitStructure[0].Src_Interval_Factor = 3;
DMA_InitStructure[0].Dest_Interval_Factor = 1;
DMA_InitStructure[0].Chaining = TO_DMA_CHANNEL_1; // <20><>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD><EFBFBD>ADC<44><43><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD>л<EFBFBD>
DMA_InitStructure[0].TCD_Address = (int32_t)&TCD_Quene[1]; // <20><><EFBFBD>ɺ<EFBFBD><C9BA><EFBFBD><EFBFBD><EFBFBD>TCD1<44><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD>
DMA_InitStructure[0].Auto_Start = DISABLE;
DMA_InitStructure[0].INT_Major = DISABLE;
DMA_InitStructure[0].INT_Half = DISABLE;
DMA_InitStructure[1].Direction = DMA_PERIPH_TO_MEMORY; // TCD1<44><31>TCD0<44><30><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>
DMA_InitStructure[1].Src_Address = (uint32_t)(&pADC->IO_CONTROL_IOUT);
DMA_InitStructure[1].Data_Width = DMA_DATA_WIDTH_16B;
DMA_InitStructure[1].Dest_Address = (uint32_t)&adcDualBuffer.BufferB[0];// ָ<>򻺴<EFBFBD><F2BBBAB4><EFBFBD>B
DMA_InitStructure[1].Data_Size = 2;
DMA_InitStructure[1].Repetition = 4;
DMA_InitStructure[1].Trans_Mode = DMA_INTERVAL_TRANSMISSION;
DMA_InitStructure[1].Src_Interval_Factor = 3;
DMA_InitStructure[1].Dest_Interval_Factor = 1;
DMA_InitStructure[1].Chaining = TO_DMA_CHANNEL_1;
DMA_InitStructure[1].TCD_Address = (int32_t)&TCD_Quene[0]; // <20><><EFBFBD>ɺ<EFBFBD><C9BA>ص<EFBFBD>TCD0
DMA_InitStructure[1].Auto_Start = DISABLE;
DMA_InitStructure[1].INT_Major = DISABLE;
DMA_InitStructure[1].INT_Half = DISABLE;
if (LHL_DMA_Init(&DMA_Handle_ADCstatus) != LHL_OK)
{
while(1); // DMA Init Error
}
/* 4. <20><><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC0<43><30>ADC1<43>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD> */
DMA_Handle_ADCcontrol.Channel = DMA_CHANNEL_1; // ע<><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>->hDMA1
DMA_Handle_ADCcontrol.Mode = DMA_DIRECT_MODE;
DMA_Handle_ADCcontrol.Request = DMA_HARDWARE_REQUEST;
DMA_Handle_ADCcontrol.Init.Direction = DMA_MEMORY_TO_PERIPH;
DMA_Handle_ADCcontrol.Init.Src_Address = (uint32_t)&ADC_DualConfig[0]; // Դ<><D4B4>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ADC˫ͨ<CBAB><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD>б<EFBFBD>
DMA_Handle_ADCcontrol.Init.Data_Width = DMA_DATA_WIDTH_16B;
DMA_Handle_ADCcontrol.Init.Dest_Address = (uint32_t)(&pADC->INTERRUPT_CONTROL_0); // Ŀ<>ĵ<EFBFBD>ַ<EFBFBD><D6B7>ADC1 CHANNEL_CFG<46>Ĵ<EFBFBD><C4B4><EFBFBD>
DMA_Handle_ADCcontrol.Init.Data_Size = 2;
DMA_Handle_ADCcontrol.Init.Repetition = SEQUENCER_COUNT; // <20><>ѭ<EFBFBD><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>
DMA_Handle_ADCcontrol.Init.Trans_Mode = DMA_INTERVAL_TRANSMISSION;
DMA_Handle_ADCcontrol.Init.Src_Interval_Factor = 1;
DMA_Handle_ADCcontrol.Init.Dest_Interval_Factor = 3;
if (LHL_DMA_Init(&DMA_Handle_ADCcontrol) != LHL_OK)
{
while(1); // DMA Init Error
}
/* 5. <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD>ʹ<EFBFBD><CAB9>DMA1<41>ж<EFBFBD> */
LHL_DMA_ITConfig(&DMA_Handle_ADCcontrol, DMA_IT_MAJOR, ENABLE); // <20><><EFBFBD><EFBFBD>DMA1<41><31><EFBFBD>ж<EFBFBD>
NVIC_EnableIRQ(DMA1_CH1_IRQn);
/* 6. <20><>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>DMA0 */
LHL_DMA_Start(&DMA_Handle_ADCstatus);
adcFlag = 0;
memset(&adcDualBuffer,0,sizeof(adcDualBuffer));
}
//<2F><>ADC<44><43><EFBFBD><EFBFBD>---------------------------------------------------------------
uint32_t ADC_ReadDualData(ADC_ID_t adcx ,uint8_t SeqChannelNum)//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD>0-8<><38><EFBFBD><EFBFBD>ȡ
{
volatile uint32_t reg_data;
volatile uint32_t uCurrentBuffer = LHL_DMA_GetDestAddress(DMA_CHANNEL_0); // <20><>ȡDMA0<41><30>ǰָ<C7B0><D6B8><EFBFBD><EFBFBD>Buffer ״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>DMA_CHANNEL_0
if (adcFlag > 0)
{
if (uCurrentBuffer < (uint32_t)adcDualBuffer.BufferB) // ͨ<><CDA8><EFBFBD><EFBFBD>ȡDMA0<41><30>Ŀ<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ݴ<EFBFBD><DDB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>Buffer
{
//The dual ADC data is stored in BufferB;
if(adcx == ADC_0) reg_data = adcDualBuffer.BufferB[SeqChannelNum].ADC0_Data ;
else reg_data = adcDualBuffer.BufferB[SeqChannelNum].ADC1_Data ;
}
else
{
//The dual ADC data is stored in BufferA
if(adcx == ADC_0) reg_data = adcDualBuffer.BufferA[SeqChannelNum].ADC0_Data ;
else reg_data = adcDualBuffer.BufferA[SeqChannelNum].ADC1_Data ;
}
reg_data = ((((reg_data & 0xFFFFFF) | ((reg_data & 0x800000) ? 0xFF000000 : 0)) >> 8) + 32768) & 0xFFFF;
adcFlag = 0;
}
return reg_data ;
}
#endif