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guishenking
2026-03-20 21:19:53 +08:00
parent 9d3b4b836f
commit 6a749331db
125 changed files with 29972 additions and 23051 deletions
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user/Main/StorageDefine.h Normal file
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#ifndef __StorageDefine_h__
#define __StorageDefine_h__
//==============================================================================
// for system Command Cache: 0x08,0x09
#define ZEROCAL_STATE 0x08
#define ZEROCAL_STATE_WIDTH 2
#define ZEROCAL_STATE_CRC (SYS_COMMAND_WIDTH-1)
// for system Command Cache: 0x0A, 0x0B
#define SYS_COMMAND 0x0A
#define SYS_COMMAND_WIDTH 2
#define SYS_COMMAND_CRC (SYS_COMMAND_WIDTH-1)
//==============================================================================
// Internal EEPROM definition (for EEPROM)
// for all parameter save: lowest bit first
#define PARAMETER_BASE 0x0D // 13
//------------------------------------------------------------------------------
#define UPGRADE_APP PARAMETER_BASE // 13
#define UPGRADE_APP_WIDTH 3
#define UPGRADE_APP_CRC (UPGRADE_APP_WIDTH-1)
//------------------------------------------------------------------------------
//#define SERIES_BASE 0x0E //(SENSOR_SN_BASE + SENSOR_SN_DEPTH) //
//#define SERIES_DEPTH 12
//------------------------------------------------------------------------------
// for MODBUS Parameter save
// All data is saved using a 16-bit storage method
#define REG_MEMORY_ADDR 0x10
#define REG_WORD_WIDTH 3
#define REG_WORD_CRC (REG_WORD_WIDTH-1)
//#define MEM_ADDR_REG_START MEM_ADDR_REG_0X30
//#define MEM_REG_START 0X30
#define MEM_ADDR_REG_0X30 REG_MEMORY_ADDR
#define MEM_ADDR_REG_0X31 ( MEM_ADDR_REG_0X30 + ( 0X31 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X32 ( MEM_ADDR_REG_0X30 + ( 0X32 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X33 ( MEM_ADDR_REG_0X30 + ( 0X33 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X34 ( MEM_ADDR_REG_0X30 + ( 0X34 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X35 ( MEM_ADDR_REG_0X30 + ( 0X35 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X36 ( MEM_ADDR_REG_0X30 + ( 0X36 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X37 ( MEM_ADDR_REG_0X30 + ( 0X37 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X38 ( MEM_ADDR_REG_0X30 + ( 0X38 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X39 ( MEM_ADDR_REG_0X30 + ( 0X39 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X3A ( MEM_ADDR_REG_0X30 + ( 0X3A - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X3B ( MEM_ADDR_REG_0X30 + ( 0X3B - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X3C ( MEM_ADDR_REG_0X30 + ( 0X3C - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X3D ( MEM_ADDR_REG_0X30 + ( 0X3D - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X3E ( MEM_ADDR_REG_0X30 + ( 0X3E - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X3F ( MEM_ADDR_REG_0X30 + ( 0X3F - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X40 ( MEM_ADDR_REG_0X30 + ( 0X40 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X41 ( MEM_ADDR_REG_0X30 + ( 0X41 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X42 ( MEM_ADDR_REG_0X30 + ( 0X42 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X43 ( MEM_ADDR_REG_0X30 + ( 0X43 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X44 ( MEM_ADDR_REG_0X30 + ( 0X44 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X45 ( MEM_ADDR_REG_0X30 + ( 0X45 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X46 ( MEM_ADDR_REG_0X30 + ( 0X46 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X47 ( MEM_ADDR_REG_0X30 + ( 0X47 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X48 ( MEM_ADDR_REG_0X30 + ( 0X48 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X49 ( MEM_ADDR_REG_0X30 + ( 0X49 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X4A ( MEM_ADDR_REG_0X30 + ( 0X4A - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X4B ( MEM_ADDR_REG_0X30 + ( 0X4B - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X4C ( MEM_ADDR_REG_0X30 + ( 0X4C - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X4D ( MEM_ADDR_REG_0X30 + ( 0X4D - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X4E ( MEM_ADDR_REG_0X30 + ( 0X4E - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X4F ( MEM_ADDR_REG_0X30 + ( 0X4F - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X50 ( MEM_ADDR_REG_0X30 + ( 0X50 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X51 ( MEM_ADDR_REG_0X30 + ( 0X51 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X52 ( MEM_ADDR_REG_0X30 + ( 0X52 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X53 ( MEM_ADDR_REG_0X30 + ( 0X53 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X54 ( MEM_ADDR_REG_0X30 + ( 0X54 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X55 ( MEM_ADDR_REG_0X30 + ( 0X55 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X56 ( MEM_ADDR_REG_0X30 + ( 0X56 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X57 ( MEM_ADDR_REG_0X30 + ( 0X57 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X58 ( MEM_ADDR_REG_0X30 + ( 0X58 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X59 ( MEM_ADDR_REG_0X30 + ( 0X59 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X5A ( MEM_ADDR_REG_0X30 + ( 0X5A - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X5B ( MEM_ADDR_REG_0X30 + ( 0X5B - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X5C ( MEM_ADDR_REG_0X30 + ( 0X5C - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X5D ( MEM_ADDR_REG_0X30 + ( 0X5D - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X5E ( MEM_ADDR_REG_0X30 + ( 0X5E - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X5F ( MEM_ADDR_REG_0X30 + ( 0X5F - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X60 ( MEM_ADDR_REG_0X30 + ( 0X60 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X61 ( MEM_ADDR_REG_0X30 + ( 0X61 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X62 ( MEM_ADDR_REG_0X30 + ( 0X62 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X63 ( MEM_ADDR_REG_0X30 + ( 0X63 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X64 ( MEM_ADDR_REG_0X30 + ( 0X64 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X65 ( MEM_ADDR_REG_0X30 + ( 0X65 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X66 ( MEM_ADDR_REG_0X30 + ( 0X66 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X67 ( MEM_ADDR_REG_0X30 + ( 0X67 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X68 ( MEM_ADDR_REG_0X30 + ( 0X68 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X69 ( MEM_ADDR_REG_0X30 + ( 0X69 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X6A ( MEM_ADDR_REG_0X30 + ( 0X6A - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X6B ( MEM_ADDR_REG_0X30 + ( 0X6B - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X6C ( MEM_ADDR_REG_0X30 + ( 0X6C - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X6D ( MEM_ADDR_REG_0X30 + ( 0X6D - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X6E ( MEM_ADDR_REG_0X30 + ( 0X6E - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X6F ( MEM_ADDR_REG_0X30 + ( 0X6F - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X70 ( MEM_ADDR_REG_0X30 + ( 0X70 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X71 ( MEM_ADDR_REG_0X30 + ( 0X71 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X72 ( MEM_ADDR_REG_0X30 + ( 0X72 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X73 ( MEM_ADDR_REG_0X30 + ( 0X73 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X74 ( MEM_ADDR_REG_0X30 + ( 0X74 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X75 ( MEM_ADDR_REG_0X30 + ( 0X75 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X76 ( MEM_ADDR_REG_0X30 + ( 0X76 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X77 ( MEM_ADDR_REG_0X30 + ( 0X77 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X78 ( MEM_ADDR_REG_0X30 + ( 0X78 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X79 ( MEM_ADDR_REG_0X30 + ( 0X79 - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X7A ( MEM_ADDR_REG_0X30 + ( 0X7A - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X7B ( MEM_ADDR_REG_0X30 + ( 0X7B - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X7C ( MEM_ADDR_REG_0X30 + ( 0X7C - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X7D ( MEM_ADDR_REG_0X30 + ( 0X7D - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X7E ( MEM_ADDR_REG_0X30 + ( 0X7E - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X7F ( MEM_ADDR_REG_0X30 + ( 0X7F - 0X30 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X80 ( MEM_ADDR_REG_0X7F + REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X81 ( MEM_ADDR_REG_0X80 + ( 0X81 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X82 ( MEM_ADDR_REG_0X80 + ( 0X82 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X83 ( MEM_ADDR_REG_0X80 + ( 0X83 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X84 ( MEM_ADDR_REG_0X80 + ( 0X84 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X85 ( MEM_ADDR_REG_0X80 + ( 0X85 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X86 ( MEM_ADDR_REG_0X80 + ( 0X86 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X87 ( MEM_ADDR_REG_0X80 + ( 0X87 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X88 ( MEM_ADDR_REG_0X80 + ( 0X88 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X89 ( MEM_ADDR_REG_0X80 + ( 0X89 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8A ( MEM_ADDR_REG_0X80 + ( 0X8A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8B ( MEM_ADDR_REG_0X80 + ( 0X8B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8C ( MEM_ADDR_REG_0X80 + ( 0X8C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8D ( MEM_ADDR_REG_0X80 + ( 0X8D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8E ( MEM_ADDR_REG_0X80 + ( 0X8E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8F ( MEM_ADDR_REG_0X80 + ( 0X8F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X90 ( MEM_ADDR_REG_0X80 + ( 0X90 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X91 ( MEM_ADDR_REG_0X80 + ( 0X91 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X92 ( MEM_ADDR_REG_0X80 + ( 0X92 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X93 ( MEM_ADDR_REG_0X80 + ( 0X93 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X94 ( MEM_ADDR_REG_0X80 + ( 0X94 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X95 ( MEM_ADDR_REG_0X80 + ( 0X95 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X96 ( MEM_ADDR_REG_0X80 + ( 0X96 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X97 ( MEM_ADDR_REG_0X80 + ( 0X97 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X98 ( MEM_ADDR_REG_0X80 + ( 0X98 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X99 ( MEM_ADDR_REG_0X80 + ( 0X99 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X9A ( MEM_ADDR_REG_0X80 + ( 0X9A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X9B ( MEM_ADDR_REG_0X80 + ( 0X9B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X9C ( MEM_ADDR_REG_0X80 + ( 0X9C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X9D ( MEM_ADDR_REG_0X80 + ( 0X9D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X9E ( MEM_ADDR_REG_0X80 + ( 0X9E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X9F ( MEM_ADDR_REG_0X80 + ( 0X9F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA0 ( MEM_ADDR_REG_0X80 + ( 0XA0 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA1 ( MEM_ADDR_REG_0X80 + ( 0XA1 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA2 ( MEM_ADDR_REG_0X80 + ( 0XA2 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA3 ( MEM_ADDR_REG_0X80 + ( 0XA3 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA4 ( MEM_ADDR_REG_0X80 + ( 0XA4 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA5 ( MEM_ADDR_REG_0X80 + ( 0XA5 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA6 ( MEM_ADDR_REG_0X80 + ( 0XA6 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA7 ( MEM_ADDR_REG_0X80 + ( 0XA7 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA8 ( MEM_ADDR_REG_0X80 + ( 0XA8 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XA9 ( MEM_ADDR_REG_0X80 + ( 0XA9 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XAA ( MEM_ADDR_REG_0X80 + ( 0XAA - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XAB ( MEM_ADDR_REG_0X80 + ( 0XAB - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XAC ( MEM_ADDR_REG_0X80 + ( 0XAC - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XAD ( MEM_ADDR_REG_0X80 + ( 0XAD - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XAE ( MEM_ADDR_REG_0X80 + ( 0XAE - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XAF ( MEM_ADDR_REG_0X80 + ( 0XAF - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB0 ( MEM_ADDR_REG_0X80 + ( 0XB0 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB1 ( MEM_ADDR_REG_0X80 + ( 0XB1 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB2 ( MEM_ADDR_REG_0X80 + ( 0XB2 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB3 ( MEM_ADDR_REG_0X80 + ( 0XB3 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB4 ( MEM_ADDR_REG_0X80 + ( 0XB4 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB5 ( MEM_ADDR_REG_0X80 + ( 0XB5 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB6 ( MEM_ADDR_REG_0X80 + ( 0XB6 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB7 ( MEM_ADDR_REG_0X80 + ( 0XB7 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB8 ( MEM_ADDR_REG_0X80 + ( 0XB8 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XB9 ( MEM_ADDR_REG_0X80 + ( 0XB9 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XBA ( MEM_ADDR_REG_0X80 + ( 0XBA - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XBB ( MEM_ADDR_REG_0X80 + ( 0XBB - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XBC ( MEM_ADDR_REG_0X80 + ( 0XBC - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XBD ( MEM_ADDR_REG_0X80 + ( 0XBD - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XBE ( MEM_ADDR_REG_0X80 + ( 0XBE - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XBF ( MEM_ADDR_REG_0X80 + ( 0XBF - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC0 ( MEM_ADDR_REG_0X80 + ( 0XC0 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC1 ( MEM_ADDR_REG_0X80 + ( 0XC1 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC2 ( MEM_ADDR_REG_0X80 + ( 0XC2 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC3 ( MEM_ADDR_REG_0X80 + ( 0XC3 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC4 ( MEM_ADDR_REG_0X80 + ( 0XC4 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC5 ( MEM_ADDR_REG_0X80 + ( 0XC5 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC6 ( MEM_ADDR_REG_0X80 + ( 0XC6 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC7 ( MEM_ADDR_REG_0X80 + ( 0XC7 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC8 ( MEM_ADDR_REG_0X80 + ( 0XC8 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XC9 ( MEM_ADDR_REG_0X80 + ( 0XC9 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XCA ( MEM_ADDR_REG_0X80 + ( 0XCA - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XCB ( MEM_ADDR_REG_0X80 + ( 0XCB - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XCC ( MEM_ADDR_REG_0X80 + ( 0XCC - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XCD ( MEM_ADDR_REG_0X80 + ( 0XCD - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XCE ( MEM_ADDR_REG_0X80 + ( 0XCE - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XCF ( MEM_ADDR_REG_0X80 + ( 0XCF - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD0 ( MEM_ADDR_REG_0X80 + ( 0XD0 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD1 ( MEM_ADDR_REG_0X80 + ( 0XD1 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD2 ( MEM_ADDR_REG_0X80 + ( 0XD2 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD3 ( MEM_ADDR_REG_0X80 + ( 0XD3 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD4 ( MEM_ADDR_REG_0X80 + ( 0XD4 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD5 ( MEM_ADDR_REG_0X80 + ( 0XD5 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD6 ( MEM_ADDR_REG_0X80 + ( 0XD6 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD7 ( MEM_ADDR_REG_0X80 + ( 0XD7 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD8 ( MEM_ADDR_REG_0X80 + ( 0XD8 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XD9 ( MEM_ADDR_REG_0X80 + ( 0XD9 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XDA ( MEM_ADDR_REG_0X80 + ( 0XDA - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XDB ( MEM_ADDR_REG_0X80 + ( 0XDB - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XDC ( MEM_ADDR_REG_0X80 + ( 0XDC - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XDD ( MEM_ADDR_REG_0X80 + ( 0XDD - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XDE ( MEM_ADDR_REG_0X80 + ( 0XDE - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XDF ( MEM_ADDR_REG_0X80 + ( 0XDF - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE0 ( MEM_ADDR_REG_0X80 + ( 0XE0 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE1 ( MEM_ADDR_REG_0X80 + ( 0XE1 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE2 ( MEM_ADDR_REG_0X80 + ( 0XE2 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE3 ( MEM_ADDR_REG_0X80 + ( 0XE3 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE4 ( MEM_ADDR_REG_0X80 + ( 0XE4 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE5 ( MEM_ADDR_REG_0X80 + ( 0XE5 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE6 ( MEM_ADDR_REG_0X80 + ( 0XE6 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE7 ( MEM_ADDR_REG_0X80 + ( 0XE7 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE8 ( MEM_ADDR_REG_0X80 + ( 0XE8 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XE9 ( MEM_ADDR_REG_0X80 + ( 0XE9 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XEA ( MEM_ADDR_REG_0X80 + ( 0XEA - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XEB ( MEM_ADDR_REG_0X80 + ( 0XEB - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XEC ( MEM_ADDR_REG_0X80 + ( 0XEC - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XED ( MEM_ADDR_REG_0X80 + ( 0XED - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XEE ( MEM_ADDR_REG_0X80 + ( 0XEE - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XEF ( MEM_ADDR_REG_0X80 + ( 0XEF - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF0 ( MEM_ADDR_REG_0X80 + ( 0XF0 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF1 ( MEM_ADDR_REG_0X80 + ( 0XF1 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF2 ( MEM_ADDR_REG_0X80 + ( 0XF2 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF3 ( MEM_ADDR_REG_0X80 + ( 0XF3 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF4 ( MEM_ADDR_REG_0X80 + ( 0XF4 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF5 ( MEM_ADDR_REG_0X80 + ( 0XF5 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF6 ( MEM_ADDR_REG_0X80 + ( 0XF6 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF7 ( MEM_ADDR_REG_0X80 + ( 0XF7 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF8 ( MEM_ADDR_REG_0X80 + ( 0XF8 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XF9 ( MEM_ADDR_REG_0X80 + ( 0XF9 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XFA ( MEM_ADDR_REG_0X80 + ( 0XFA - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XFB ( MEM_ADDR_REG_0X80 + ( 0XFB - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XFC ( MEM_ADDR_REG_0X80 + ( 0XFC - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XFD ( MEM_ADDR_REG_0X80 + ( 0XFD - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XFE ( MEM_ADDR_REG_0X80 + ( 0XFE - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0XFF ( MEM_ADDR_REG_0X80 + ( 0XFF - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X100 ( MEM_ADDR_REG_0X80 + ( 0X100 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X101 ( MEM_ADDR_REG_0X80 + ( 0X101 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X102 ( MEM_ADDR_REG_0X80 + ( 0X102 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X103 ( MEM_ADDR_REG_0X80 + ( 0X103 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X104 ( MEM_ADDR_REG_0X80 + ( 0X104 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X105 ( MEM_ADDR_REG_0X80 + ( 0X105 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X106 ( MEM_ADDR_REG_0X80 + ( 0X106 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X107 ( MEM_ADDR_REG_0X80 + ( 0X107 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X108 ( MEM_ADDR_REG_0X80 + ( 0X108 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X109 ( MEM_ADDR_REG_0X80 + ( 0X109 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X10A ( MEM_ADDR_REG_0X80 + ( 0X10A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X10B ( MEM_ADDR_REG_0X80 + ( 0X10B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X10C ( MEM_ADDR_REG_0X80 + ( 0X10C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X10D ( MEM_ADDR_REG_0X80 + ( 0X10D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X10E ( MEM_ADDR_REG_0X80 + ( 0X10E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X10F ( MEM_ADDR_REG_0X80 + ( 0X10F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X110 ( MEM_ADDR_REG_0X80 + ( 0X110 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X111 ( MEM_ADDR_REG_0X80 + ( 0X111 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X112 ( MEM_ADDR_REG_0X80 + ( 0X112 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X113 ( MEM_ADDR_REG_0X80 + ( 0X113 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X114 ( MEM_ADDR_REG_0X80 + ( 0X114 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X115 ( MEM_ADDR_REG_0X80 + ( 0X115 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X116 ( MEM_ADDR_REG_0X80 + ( 0X116 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X117 ( MEM_ADDR_REG_0X80 + ( 0X117 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X118 ( MEM_ADDR_REG_0X80 + ( 0X118 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X119 ( MEM_ADDR_REG_0X80 + ( 0X119 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X11A ( MEM_ADDR_REG_0X80 + ( 0X11A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X11B ( MEM_ADDR_REG_0X80 + ( 0X11B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X11C ( MEM_ADDR_REG_0X80 + ( 0X11C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X11D ( MEM_ADDR_REG_0X80 + ( 0X11D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X11E ( MEM_ADDR_REG_0X80 + ( 0X11E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X11F ( MEM_ADDR_REG_0X80 + ( 0X11F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X120 ( MEM_ADDR_REG_0X80 + ( 0X120 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X121 ( MEM_ADDR_REG_0X80 + ( 0X121 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X122 ( MEM_ADDR_REG_0X80 + ( 0X122 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X123 ( MEM_ADDR_REG_0X80 + ( 0X123 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X124 ( MEM_ADDR_REG_0X80 + ( 0X124 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X125 ( MEM_ADDR_REG_0X80 + ( 0X125 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X126 ( MEM_ADDR_REG_0X80 + ( 0X126 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X127 ( MEM_ADDR_REG_0X80 + ( 0X127 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X128 ( MEM_ADDR_REG_0X80 + ( 0X128 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X129 ( MEM_ADDR_REG_0X80 + ( 0X129 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X12A ( MEM_ADDR_REG_0X80 + ( 0X12A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X12B ( MEM_ADDR_REG_0X80 + ( 0X12B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X12C ( MEM_ADDR_REG_0X80 + ( 0X12C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X12D ( MEM_ADDR_REG_0X80 + ( 0X12D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X12E ( MEM_ADDR_REG_0X80 + ( 0X12E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X12F ( MEM_ADDR_REG_0X80 + ( 0X12F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X130 ( MEM_ADDR_REG_0X80 + ( 0X130 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X131 ( MEM_ADDR_REG_0X80 + ( 0X131 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X132 ( MEM_ADDR_REG_0X80 + ( 0X132 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X133 ( MEM_ADDR_REG_0X80 + ( 0X133 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X134 ( MEM_ADDR_REG_0X80 + ( 0X134 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X135 ( MEM_ADDR_REG_0X80 + ( 0X135 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X136 ( MEM_ADDR_REG_0X80 + ( 0X136 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X137 ( MEM_ADDR_REG_0X80 + ( 0X137 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X138 ( MEM_ADDR_REG_0X80 + ( 0X138 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X139 ( MEM_ADDR_REG_0X80 + ( 0X139 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X13A ( MEM_ADDR_REG_0X80 + ( 0X13A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X13B ( MEM_ADDR_REG_0X80 + ( 0X13B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X13C ( MEM_ADDR_REG_0X80 + ( 0X13C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X13D ( MEM_ADDR_REG_0X80 + ( 0X13D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X13E ( MEM_ADDR_REG_0X80 + ( 0X13E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X13F ( MEM_ADDR_REG_0X80 + ( 0X13F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X140 ( MEM_ADDR_REG_0X80 + ( 0X140 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X141 ( MEM_ADDR_REG_0X80 + ( 0X141 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X142 ( MEM_ADDR_REG_0X80 + ( 0X142 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X143 ( MEM_ADDR_REG_0X80 + ( 0X143 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X144 ( MEM_ADDR_REG_0X80 + ( 0X144 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X145 ( MEM_ADDR_REG_0X80 + ( 0X145 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X146 ( MEM_ADDR_REG_0X80 + ( 0X146 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X147 ( MEM_ADDR_REG_0X80 + ( 0X147 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X148 ( MEM_ADDR_REG_0X80 + ( 0X148 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X149 ( MEM_ADDR_REG_0X80 + ( 0X149 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X14A ( MEM_ADDR_REG_0X80 + ( 0X14A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X14B ( MEM_ADDR_REG_0X80 + ( 0X14B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X14C ( MEM_ADDR_REG_0X80 + ( 0X14C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X14D ( MEM_ADDR_REG_0X80 + ( 0X14D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X14E ( MEM_ADDR_REG_0X80 + ( 0X14E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X14F ( MEM_ADDR_REG_0X80 + ( 0X14F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X150 ( MEM_ADDR_REG_0X80 + ( 0X150 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X151 ( MEM_ADDR_REG_0X80 + ( 0X151 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X152 ( MEM_ADDR_REG_0X80 + ( 0X152 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X153 ( MEM_ADDR_REG_0X80 + ( 0X153 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X154 ( MEM_ADDR_REG_0X80 + ( 0X154 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X155 ( MEM_ADDR_REG_0X80 + ( 0X155 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X156 ( MEM_ADDR_REG_0X80 + ( 0X156 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X157 ( MEM_ADDR_REG_0X80 + ( 0X157 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X158 ( MEM_ADDR_REG_0X80 + ( 0X158 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X159 ( MEM_ADDR_REG_0X80 + ( 0X159 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X15A ( MEM_ADDR_REG_0X80 + ( 0X15A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X15B ( MEM_ADDR_REG_0X80 + ( 0X15B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X15C ( MEM_ADDR_REG_0X80 + ( 0X15C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X15D ( MEM_ADDR_REG_0X80 + ( 0X15D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X15E ( MEM_ADDR_REG_0X80 + ( 0X15E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X15F ( MEM_ADDR_REG_0X80 + ( 0X15F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X160 ( MEM_ADDR_REG_0X80 + ( 0X160 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X161 ( MEM_ADDR_REG_0X80 + ( 0X161 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X162 ( MEM_ADDR_REG_0X80 + ( 0X162 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X163 ( MEM_ADDR_REG_0X80 + ( 0X163 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X164 ( MEM_ADDR_REG_0X80 + ( 0X164 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X165 ( MEM_ADDR_REG_0X80 + ( 0X165 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X166 ( MEM_ADDR_REG_0X80 + ( 0X166 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X167 ( MEM_ADDR_REG_0X80 + ( 0X167 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X168 ( MEM_ADDR_REG_0X80 + ( 0X168 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X169 ( MEM_ADDR_REG_0X80 + ( 0X169 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X16A ( MEM_ADDR_REG_0X80 + ( 0X16A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X16B ( MEM_ADDR_REG_0X80 + ( 0X16B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X16C ( MEM_ADDR_REG_0X80 + ( 0X16C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X16D ( MEM_ADDR_REG_0X80 + ( 0X16D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X16E ( MEM_ADDR_REG_0X80 + ( 0X16E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X16F ( MEM_ADDR_REG_0X80 + ( 0X16F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X170 ( MEM_ADDR_REG_0X80 + ( 0X170 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X171 ( MEM_ADDR_REG_0X80 + ( 0X171 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X172 ( MEM_ADDR_REG_0X80 + ( 0X172 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X173 ( MEM_ADDR_REG_0X80 + ( 0X173 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X174 ( MEM_ADDR_REG_0X80 + ( 0X174 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X175 ( MEM_ADDR_REG_0X80 + ( 0X175 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X176 ( MEM_ADDR_REG_0X80 + ( 0X176 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X177 ( MEM_ADDR_REG_0X80 + ( 0X177 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X178 ( MEM_ADDR_REG_0X80 + ( 0X178 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X179 ( MEM_ADDR_REG_0X80 + ( 0X179 - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X17A ( MEM_ADDR_REG_0X80 + ( 0X17A - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X17B ( MEM_ADDR_REG_0X80 + ( 0X17B - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X17C ( MEM_ADDR_REG_0X80 + ( 0X17C - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X17D ( MEM_ADDR_REG_0X80 + ( 0X17D - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X17E ( MEM_ADDR_REG_0X80 + ( 0X17E - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X17F ( MEM_ADDR_REG_0X80 + ( 0X17F - 0X80 ) * REG_WORD_WIDTH )
#define MEM_ADDR_USER_REG_END ( MEM_ADDR_REG_0X17F + REG_WORD_WIDTH)
//--------------------------------------------------------------------------------
#define MAP_SET1 MEM_ADDR_REG_0X100
#define MAP_SET1_WORD REG_WORD_WIDTH
#define REG_MEM_ADDR_END (MEM_ADDR_REG_0X17F + REG_WORD_WIDTH)
//#define REG_WORD_MEM_MAX ((REG_MEM_ADDR_END - MEM_ADDR_REG_START)/REG_WORD_WIDTH)
//--------------------------------------------------------------------------------
// for Internal parameter save
// for 16bit parameter
// max 128
#define MEM_ADDR_WORD_REG_START MEM_ADDR_USER_REG_END
#define MEM_ADDR_REG_0X8210 MEM_ADDR_WORD_REG_START
#define MEM_ADDR_REG_0X8211 ( MEM_ADDR_REG_0X8210 + ( 0X8211 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8212 ( MEM_ADDR_REG_0X8210 + ( 0X8212 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8213 ( MEM_ADDR_REG_0X8210 + ( 0X8213 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8214 ( MEM_ADDR_REG_0X8210 + ( 0X8214 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8215 ( MEM_ADDR_REG_0X8210 + ( 0X8215 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8216 ( MEM_ADDR_REG_0X8210 + ( 0X8216 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8217 ( MEM_ADDR_REG_0X8210 + ( 0X8217 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8218 ( MEM_ADDR_REG_0X8210 + ( 0X8218 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8219 ( MEM_ADDR_REG_0X8210 + ( 0X8219 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X821A ( MEM_ADDR_REG_0X8210 + ( 0X821A - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X821B ( MEM_ADDR_REG_0X8210 + ( 0X821B - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X821C ( MEM_ADDR_REG_0X8210 + ( 0X821C - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X821D ( MEM_ADDR_REG_0X8210 + ( 0X821D - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X821E ( MEM_ADDR_REG_0X8210 + ( 0X821E - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X821F ( MEM_ADDR_REG_0X8210 + ( 0X821F - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8220 ( MEM_ADDR_REG_0X8210 + ( 0X8220 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8221 ( MEM_ADDR_REG_0X8210 + ( 0X8221 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8222 ( MEM_ADDR_REG_0X8210 + ( 0X8222 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8223 ( MEM_ADDR_REG_0X8210 + ( 0X8223 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8224 ( MEM_ADDR_REG_0X8210 + ( 0X8224 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8225 ( MEM_ADDR_REG_0X8210 + ( 0X8225 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8226 ( MEM_ADDR_REG_0X8210 + ( 0X8226 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8227 ( MEM_ADDR_REG_0X8210 + ( 0X8227 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8228 ( MEM_ADDR_REG_0X8210 + ( 0X8228 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8229 ( MEM_ADDR_REG_0X8210 + ( 0X8229 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X822A ( MEM_ADDR_REG_0X8210 + ( 0X822A - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X822B ( MEM_ADDR_REG_0X8210 + ( 0X822B - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X822C ( MEM_ADDR_REG_0X8210 + ( 0X822C - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X822D ( MEM_ADDR_REG_0X8210 + ( 0X822D - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X822E ( MEM_ADDR_REG_0X8210 + ( 0X822E - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X822F ( MEM_ADDR_REG_0X8210 + ( 0X822F - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8230 ( MEM_ADDR_REG_0X8210 + ( 0X8230 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8231 ( MEM_ADDR_REG_0X8210 + ( 0X8231 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8232 ( MEM_ADDR_REG_0X8210 + ( 0X8232 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8233 ( MEM_ADDR_REG_0X8210 + ( 0X8233 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8234 ( MEM_ADDR_REG_0X8210 + ( 0X8234 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8235 ( MEM_ADDR_REG_0X8210 + ( 0X8235 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8236 ( MEM_ADDR_REG_0X8210 + ( 0X8236 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8237 ( MEM_ADDR_REG_0X8210 + ( 0X8237 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8238 ( MEM_ADDR_REG_0X8210 + ( 0X8238 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8239 ( MEM_ADDR_REG_0X8210 + ( 0X8239 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X823A ( MEM_ADDR_REG_0X8210 + ( 0X823A - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X823B ( MEM_ADDR_REG_0X8210 + ( 0X823B - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X823C ( MEM_ADDR_REG_0X8210 + ( 0X823C - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X823D ( MEM_ADDR_REG_0X8210 + ( 0X823D - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X823E ( MEM_ADDR_REG_0X8210 + ( 0X823E - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X823F ( MEM_ADDR_REG_0X8210 + ( 0X823F - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8240 ( MEM_ADDR_REG_0X8210 + ( 0X8240 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8241 ( MEM_ADDR_REG_0X8210 + ( 0X8241 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8242 ( MEM_ADDR_REG_0X8210 + ( 0X8242 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8243 ( MEM_ADDR_REG_0X8210 + ( 0X8243 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8244 ( MEM_ADDR_REG_0X8210 + ( 0X8244 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8245 ( MEM_ADDR_REG_0X8210 + ( 0X8245 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8246 ( MEM_ADDR_REG_0X8210 + ( 0X8246 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8247 ( MEM_ADDR_REG_0X8210 + ( 0X8247 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8248 ( MEM_ADDR_REG_0X8210 + ( 0X8248 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8249 ( MEM_ADDR_REG_0X8210 + ( 0X8249 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X824A ( MEM_ADDR_REG_0X8210 + ( 0X824A - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X824B ( MEM_ADDR_REG_0X8210 + ( 0X824B - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X824C ( MEM_ADDR_REG_0X8210 + ( 0X824C - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X824D ( MEM_ADDR_REG_0X8210 + ( 0X824D - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X824E ( MEM_ADDR_REG_0X8210 + ( 0X824E - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X824F ( MEM_ADDR_REG_0X8210 + ( 0X824F - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8250 ( MEM_ADDR_REG_0X8210 + ( 0X8250 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8251 ( MEM_ADDR_REG_0X8210 + ( 0X8251 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8252 ( MEM_ADDR_REG_0X8210 + ( 0X8252 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8253 ( MEM_ADDR_REG_0X8210 + ( 0X8253 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8254 ( MEM_ADDR_REG_0X8210 + ( 0X8254 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8255 ( MEM_ADDR_REG_0X8210 + ( 0X8255 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8256 ( MEM_ADDR_REG_0X8210 + ( 0X8256 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8257 ( MEM_ADDR_REG_0X8210 + ( 0X8257 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8258 ( MEM_ADDR_REG_0X8210 + ( 0X8258 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8259 ( MEM_ADDR_REG_0X8210 + ( 0X8259 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X825A ( MEM_ADDR_REG_0X8210 + ( 0X825A - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X825B ( MEM_ADDR_REG_0X8210 + ( 0X825B - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X825C ( MEM_ADDR_REG_0X8210 + ( 0X825C - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X825D ( MEM_ADDR_REG_0X8210 + ( 0X825D - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X825E ( MEM_ADDR_REG_0X8210 + ( 0X825E - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X825F ( MEM_ADDR_REG_0X8210 + ( 0X825F - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8260 ( MEM_ADDR_REG_0X8210 + ( 0X8260 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8261 ( MEM_ADDR_REG_0X8210 + ( 0X8261 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8262 ( MEM_ADDR_REG_0X8210 + ( 0X8262 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8263 ( MEM_ADDR_REG_0X8210 + ( 0X8263 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8264 ( MEM_ADDR_REG_0X8210 + ( 0X8264 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8265 ( MEM_ADDR_REG_0X8210 + ( 0X8265 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8266 ( MEM_ADDR_REG_0X8210 + ( 0X8266 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8267 ( MEM_ADDR_REG_0X8210 + ( 0X8267 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8268 ( MEM_ADDR_REG_0X8210 + ( 0X8268 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8269 ( MEM_ADDR_REG_0X8210 + ( 0X8269 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X826A ( MEM_ADDR_REG_0X8210 + ( 0X826A - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X826B ( MEM_ADDR_REG_0X8210 + ( 0X826B - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X826C ( MEM_ADDR_REG_0X8210 + ( 0X826C - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X826D ( MEM_ADDR_REG_0X8210 + ( 0X826D - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X826E ( MEM_ADDR_REG_0X8210 + ( 0X826E - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X826F ( MEM_ADDR_REG_0X8210 + ( 0X826F - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8270 ( MEM_ADDR_REG_0X8210 + ( 0X8270 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8271 ( MEM_ADDR_REG_0X8210 + ( 0X8271 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8272 ( MEM_ADDR_REG_0X8210 + ( 0X8272 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8273 ( MEM_ADDR_REG_0X8210 + ( 0X8273 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8274 ( MEM_ADDR_REG_0X8210 + ( 0X8274 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8275 ( MEM_ADDR_REG_0X8210 + ( 0X8275 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8276 ( MEM_ADDR_REG_0X8210 + ( 0X8276 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8277 ( MEM_ADDR_REG_0X8210 + ( 0X8277 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8278 ( MEM_ADDR_REG_0X8210 + ( 0X8278 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X8279 ( MEM_ADDR_REG_0X8210 + ( 0X8279 - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X827A ( MEM_ADDR_REG_0X8210 + ( 0X827A - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X827B ( MEM_ADDR_REG_0X8210 + ( 0X827B - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X827C ( MEM_ADDR_REG_0X8210 + ( 0X827C - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X827D ( MEM_ADDR_REG_0X8210 + ( 0X827D - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X827E ( MEM_ADDR_REG_0X8210 + ( 0X827E - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_REG_0X827F ( MEM_ADDR_REG_0X8210 + ( 0X827F - 0X8210 ) * REG_WORD_WIDTH )
#define MEM_ADDR_WORD_REG_END ( MEM_ADDR_REG_0X827F + REG_WORD_WIDTH)
//#define REG_INT_WORD_MEM_MAX ((REG_INT_WORD_MEM_ADDR_END - REG_INT_WORD_MEM_ADDR_START)/REG_WORD_WIDTH)
//--------------------------------------------------------------------------------
// for Internal parameter save
// for 32bit parameter
// max 64
#define REG_DWORD_WIDTH 5
//#define REG_DWORD_CRC (REG_DWORD_WIDTH - 1)
#define MEM_ADDR_DWORD_REG_START MEM_ADDR_WORD_REG_END
#define MEM_ADDR_REG_0X8280 MEM_ADDR_WORD_REG_END
#define MEM_ADDR_REG_0X8282 (MEM_ADDR_REG_0X8280 + ((0X8282 - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X8284 (MEM_ADDR_REG_0X8280 + ((0X8284 - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X8286 (MEM_ADDR_REG_0X8280 + ((0X8286 - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X8288 (MEM_ADDR_REG_0X8280 + ((0X8288 - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X828A (MEM_ADDR_REG_0X8280 + ((0X828A - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X828C (MEM_ADDR_REG_0X8280 + ((0X828C - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X828E (MEM_ADDR_REG_0X8280 + ((0X828E - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X8290 (MEM_ADDR_REG_0X8280 + ((0X8290 - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X8292 (MEM_ADDR_REG_0X8280 + ((0X8292 - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X8294 (MEM_ADDR_REG_0X8280 + ((0X8294 - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X8296 (MEM_ADDR_REG_0X8280 + ((0X8296 - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X8298 (MEM_ADDR_REG_0X8280 + ((0X8298 - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X829A (MEM_ADDR_REG_0X8280 + ((0X829A - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X829C (MEM_ADDR_REG_0X8280 + ((0X829C - 0X8280)>>1) * REG_DWORD_WIDTH)
#define MEM_ADDR_REG_0X829E (MEM_ADDR_REG_0X8280 + ((0X829E - 0X8280)>>1) * REG_DWORD_WIDTH)
#define REG_INT_DWORD_MEM_ADDR_END (MEM_ADDR_REG_0X829E + REG_DWORD_WIDTH)
//#define REG_INT_DWORD_MEM_MAX ((REG_INT_DWORD_MEM_ADDR_END - REG_INT_DWORD_MEM_ADDR_START)/REG_DWORD_WIDTH)
#define PARAMETER_DEFINE_END REG_INT_DWORD_MEM_ADDR_END
//***************************************************************************************************************************
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6>ϵ<EFBFBD><CFB5>
//MEM_ADDR_REG_0X30 ------- INX_030
//MEM_ADDR_REG_0X8200 ------- REG_0X8200
//MEM_ADDR_REG_0X853F ------- REG_0X8500
//--------------0x010->0X400 ǰ<><C7B0><EFBFBD>ֽڴ<D6BD><DAB4><EFBFBD>_<EFBFBD>û<EFBFBD><C3BB>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ0x400<30><30>ʼ<EFBFBD><CABC>
//--------------0X400->0x580 128<32><38>u16ռ128*3=384<38>ֽ<EFBFBD>
//--------------0X580->0x6C0 64<36><34>u32ռ64*5=320<32>ֽ<EFBFBD> 0x10+1712 byte
//******************************************************************************
#if(PARAMETER_DEFINE_END > 0x0600)
#error The defined address is out of range: PARAMETER_DEFINE_END
#endif
//******************************************************************************
// 0x0200 DCOEF define
#define PARAMETER_BASE_0X0200 0x0600
//#define DCOEF_NUM 0x0200 // EEPROM address for the number of intervals for device coefficients
//#define DCOEF_NUM_WIDTH 2 // 2byte
//#define DCOEF_NUM_CRC (DCOEF_NUM_WIDTH-1)
//#define DCOEF_UNIT //(DCOEF_NUM+DCOEF_NUM_WIDTH)
//#define DCOEF_UNIT_WIDTH 2
//#define DCOEF_UNIT_CRC (DCOEF_UNIT_WIDTH-1)
#define DCOEF_BASE 0x0600 // (DCOEF_UNIT+DCOEF_UNIT_WIDTH)
#define DCOEF_DATA_WIDTH 6
#define DCOEF_WIDTH 7 // DCOEF_WIDTH byte required for each device coefficient data
#define DCOEF_CRC (DCOEF_WIDTH-1)
#define DCOEF_MAX 20 // the max allowable number of intervals for for device coefficients
#define DCOEF_NODE_WIDTH 5
#define DCOEF_VALUE_WIDTH 3
#define DCOEF_DEFINE_NODE ( DCOEF_BASE + DCOEF_WIDTH * DCOEF_MAX )
//******************************************************************************
#if(DCOEF_DEFINE_NODE > 0X0700)
#error The defined address is out of range: DCOEF_DEFINE_NODE
#endif
//******************************************************************************
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><C2B6><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD>(Ԥ<><D4A4>256<35>ֽ<EFBFBD>)
#define TACURVE_NUM 0x700
#define TACURVE_NUM_WIDTH 2
#define TACURVE_NUM_CRC (TACURVE_NUM_WIDTH-1)
#define TACURVE_DATA_BASE (TACURVE_NUM + TACURVE_NUM_WIDTH)
#define TACURVE_DATA_WIDTH 5
#define TACURVE_DATA_CRC (TACURVE_DATA_WIDTH-1)
#define CURVE_DATA_MAX 36
//------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD>ԭʼ<D4AD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD>(Ԥ<><D4A4>256<35>ֽ<EFBFBD>)
#define ATYPECURVE_NUM 0x800
#define ATYPECURVE_NUM_WIDTH 2 // 2byte
#define ATYPECURVE_NUM_CRC (ATYPECURVE_NUM_WIDTH-1) // 2byte
#define ATYPECURVE_DATA_BASE (ATYPECURVE_NUM+ATYPECURVE_NUM_WIDTH)
#define ATYPECURVE_DATA_WIDTH 5
#define ATYPECURVE_DATA_CRC (ATYPECURVE_DATA_WIDTH-1)
#define ATYPECURVE_DATA_END (ATYPECURVE_DATA_BASE + ATYPECURVE_DATA_WIDTH * CURVE_DATA_MAX)
//******************************************************************************
#if(ATYPECURVE_DATA_END > 0X0900)
#error The defined address is out of range: ATYPECURVE_DATA_END
#endif
//******************************************************************************
// <20><><EFBFBD><EFBFBD>ԭʼ<D4AD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD>(Ԥ<><D4A4>256<35>ֽ<EFBFBD>)
#define REC_ACC_BASE 0x0900 // the start EEPROM address of acc data
#define REC_ACC_WIDTH 14 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32>
#define REC_ACC_DEPTH 4
#define ACC_BLOCK_WIDTH 7 // 0x100(256) + 14*4 = 0x138(312) ÿ<><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD>
#define ACC_BLOCK2_START 0x0940 // 0x180(256) + 14*4 = 0x1B8
#define REC_ACC_END (ACC_BLOCK2_START + REC_ACC_WIDTH * REC_ACC_DEPTH
//------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD>ԭʼ<D4AD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD>(Ԥ<><D4A4>256<35>ֽ<EFBFBD>)
#define BASIC_DATA_BASE 0x980
#define BASIC_DATA_MAX ANX
#define BASIC_DATA_BYTE_MAX (BASIC_DATA_MAX*2)
//******************************************************************************
// calibration data start address
//******************************************************************************
#define CALI_DATA_ADDR 0x1000 // for EEPROM store calibration data start addr
//******************************************************************************
//==============================================================================
// for BootLoader and upgrade programm
//==============================================================================
// for information flash
#define FLASH_INFO_OFFSET 0x1800 // segment D
//#define PARA_LEN (UPGRADE_APP_WIDTH+PROTOCOL_WIDTH+BAUD_RATE_WIDTH+SLAVER_ADDR_WIDTH)
#define PARA_LEN (UPGRADE_APP_WIDTH+PROTOCOL_WIDTH+SLAVER_ADDR_WIDTH)
#endif