NULL
This commit is contained in:
443
startup/IAR/startup_lh32m0S3x.s
Executable file
443
startup/IAR/startup_lh32m0S3x.s
Executable file
@@ -0,0 +1,443 @@
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;******************** (C) COPYRIGHT 2022 LegendSemi *******************
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;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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||||
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
|
||||
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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;*******************************************************************************
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; 0: window Watchdog Timer
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DCD PVD_IRQHandler ; 1:
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DCD 0 ; 2:
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DCD RTC_IRQHandler ; 3: RTC
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DCD FLASH_IRQHandler ; 4: FLASH
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DCD RCC_IRQHandler ; 5: RCC
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DCD EXTI0_IRQHandler ; 6: EXTI0
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DCD EXTI1_IRQHandler ; 7: EXTI1
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DCD EXTI2_IRQHandler ; 8: EXTI2
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DCD EXTI3_IRQHandler ; 9: EXTI3
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DCD EXTI4_IRQHandler ; 10: EXTI4
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DCD DMA_CH1_IRQHandler ; 11:
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DCD SPI1_IRQHandler ; 12:
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DCD UART1_IRQHandler ; 13:
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DCD RTCAlarm_IRQHandler ; 14:
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DCD QSPI_IRQHandler ; 15:
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DCD BEEPER_IRQHandler ; 16:
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DCD LCD_IRQHandler ; 17:
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DCD ADC_IRQHandler ; 18:
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DCD 0 ; 19:
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DCD ADC_SEQ_IRQHandler ; 20:
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DCD 0 ; 21:
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DCD LED_IRQHandler ; 22:
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DCD EXINT7_5_IRQHandler ; 23:
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DCD TIMER1_BRK_IRQHandler ; 24:
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DCD TIMER1_UP_IRQHandler ; 25:
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DCD TIMER1_TRIG_COM_IRQHandler ; 26:
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DCD TIMER1_CC_IRQHandler ; 27:
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DCD TIMER2_IRQHandler ; 28:
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DCD 0 ; 29:
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DCD I2C_ER_IRQHandler ; 30:
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DCD I2C_EV_IRQHandler ; 31:
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DCD 0 ; 32:
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DCD 0 ; 33:
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DCD 0 ; 34:
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DCD 0 ; 35:
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DCD 0 ; 36:
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DCD 0 ; 37:
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DCD 0 ; 38:
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DCD 0 ; 39:
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DCD 0 ; 40:
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DCD 0 ; 41:
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DCD 0 ; 42:
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DCD 0 ; 43:
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DCD 0 ; 44:
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DCD 0 ; 45:
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DCD 0 ; 46:
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DCD 0 ; 47:
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DCD 0 ; 48:
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DCD 0 ; 49:
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DCD 0 ; 50:
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DCD 0 ; 51:
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DCD 0 ; 52:
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DCD 0 ; 53:
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DCD 0 ; 54:
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DCD 0 ; 55:
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DCD 0 ; 56:
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER:NOROOT(2)
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Reset_Handler
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MOVS.N R1,#0
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LDR R0,[R1]
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MOV SP,R0
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK MemManage_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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MemManage_Handler
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B MemManage_Handler
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PUBWEAK BusFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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BusFault_Handler
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B BusFault_Handler
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PUBWEAK UsageFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UsageFault_Handler
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B UsageFault_Handler
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||||
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B SVC_Handler
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||||
PUBWEAK DebugMon_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DebugMon_Handler
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B DebugMon_Handler
|
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|
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PUBWEAK PendSV_Handler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B PendSV_Handler
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||||
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||||
PUBWEAK SysTick_Handler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
SysTick_Handler
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||||
B SysTick_Handler
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||||
|
||||
PUBWEAK WWDG_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
WWDG_IRQHandler
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||||
B WWDG_IRQHandler
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||||
|
||||
PUBWEAK PVD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PVD_IRQHandler
|
||||
B PVD_IRQHandler
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||||
|
||||
PUBWEAK RTCAlarm_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTCAlarm_IRQHandler
|
||||
B RTCAlarm_IRQHandler
|
||||
|
||||
PUBWEAK QSPI_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QSPI_IRQHandler
|
||||
B QSPI_IRQHandler
|
||||
|
||||
PUBWEAK BEEPER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BEEPER_IRQHandler
|
||||
B BEEPER_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK ADC_SEQ_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC_SEQ_IRQHandler
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||||
B ADC_SEQ_IRQHandler
|
||||
|
||||
PUBWEAK LED_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
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||||
LED_IRQHandler
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||||
B LED_IRQHandler
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||||
|
||||
PUBWEAK EXINT7_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT7_5_IRQHandler
|
||||
B EXINT7_5_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_BRK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_BRK_IRQHandler
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||||
B TIMER1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_UP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_UP_IRQHandler
|
||||
B TIMER1_UP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_TRIG_COM_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_TRIG_COM_IRQHandler
|
||||
B TIMER1_TRIG_COM_IRQHandler
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||||
|
||||
|
||||
PUBWEAK TIMER1_CC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_CC_IRQHandler
|
||||
B TIMER1_CC_IRQHandler
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||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC_IRQHandler
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||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FLASH_IRQHandler
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||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
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||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA_CH1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA_CH1_IRQHandler
|
||||
B DMA_CH1_IRQHandler
|
||||
|
||||
PUBWEAK DMA_CH2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA_CH2_IRQHandler
|
||||
B DMA_CH2_IRQHandler
|
||||
|
||||
PUBWEAK DMA_CH3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA_CH3_IRQHandler
|
||||
B DMA_CH3_IRQHandler
|
||||
|
||||
PUBWEAK DMA_CH4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA_CH4_IRQHandler
|
||||
B DMA_CH4_IRQHandler
|
||||
|
||||
PUBWEAK DMA_CH5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA_CH5_IRQHandler
|
||||
B DMA_CH5_IRQHandler
|
||||
|
||||
PUBWEAK DMA_CH6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA_CH6_IRQHandler
|
||||
B DMA_CH6_IRQHandler
|
||||
|
||||
PUBWEAK DMA_CH7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA_CH7_IRQHandler
|
||||
B DMA_CH7_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXINT9_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT9_5_IRQHandler
|
||||
B EXINT9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER4_IRQHandler
|
||||
B TIMER4_IRQHandler
|
||||
|
||||
PUBWEAK I2C_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C_EV_IRQHandler
|
||||
B I2C_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C_ER_IRQHandler
|
||||
B I2C_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK UART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART1_IRQHandler
|
||||
B UART1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK EXTI17_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI17_IRQHandler
|
||||
B EXTI17_IRQHandler
|
||||
|
||||
PUBWEAK EXTI18_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI18_IRQHandler
|
||||
B EXTI18_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER5_IRQHandler
|
||||
B TIMER5_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK CACHE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CACHE_IRQHandler
|
||||
B CACHE_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_CH1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_CH1_IRQHandler
|
||||
B DMA2_CH1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_CH2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_CH2_IRQHandler
|
||||
B DMA2_CH2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_CH3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_CH3_IRQHandler
|
||||
B DMA2_CH3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_CH4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_CH4_IRQHandler
|
||||
B DMA2_CH4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_CH5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_CH5_IRQHandler
|
||||
B DMA2_CH5_IRQHandler
|
||||
|
||||
PUBWEAK DIG_COMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DIG_COMP_IRQHandler
|
||||
B DIG_COMP_IRQHandler
|
||||
|
||||
PUBWEAK MDIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MDIO_IRQHandler
|
||||
B MDIO_IRQHandler
|
||||
|
||||
PUBWEAK PLA0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PLA0_IRQHandler
|
||||
B PLA0_IRQHandler
|
||||
|
||||
PUBWEAK PLA2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PLA2_IRQHandler
|
||||
B PLA2_IRQHandler
|
||||
|
||||
END
|
||||
/******************* (C) COPYRIGHT 2022 LegendSemi *****END OF FILE****/
|
||||
271
startup/KEIL/startup_lh32m0g3x.s
Executable file
271
startup/KEIL/startup_lh32m0g3x.s
Executable file
@@ -0,0 +1,271 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file startup_ARMCM0.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM0 Device Series
|
||||
; * @version V1.08
|
||||
; * @version 23. November 2012
|
||||
; *
|
||||
; * @note
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
;/* Copyright (c) 2011 - 2012 ARM LIMITED
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000800
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000 ;!!!Make sure if need: 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY ;
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD 0 ; Reserved
|
||||
DCD PVD_IRQHandler ; PVD 1:
|
||||
DCD ADC_ERR_IRQHandler ;ADC ERROR 2:
|
||||
DCD RTC_IRQHandler ; 3: RTC
|
||||
DCD CROSSLINK_IRQHandler ;CROSSLINK 4:
|
||||
DCD RCC_IRQHandler ; 5: RCC
|
||||
DCD EXTI0_1_IRQHandler ;EXTI Line 0,1 6:
|
||||
DCD EXTI2_3_IRQHandler ;EXTI Line 2,3 7:
|
||||
DCD EXTI4_7_IRQHandler ;EXTI Line 4..7 8:
|
||||
DCD DMA1_CH0_IRQHandler ;DMA1_Channel 0 9
|
||||
DCD DMA1_CH1_IRQHandler ;DMA1_Channel 1 10:
|
||||
DCD DMA1_CH2_3_IRQHandler ;DMA1_Channel 2,3 11:
|
||||
DCD SPI0_IRQHandler ;SPI0 12:
|
||||
DCD UART0_IRQHandler ;UART0 13:
|
||||
DCD RTCAlarm_IRQHandler ;RTCAlarm 14:
|
||||
DCD QSPI_IRQHandlern ;QSPI FLASH 15:
|
||||
DCD MIO_IRQHandler ;MIO 16:
|
||||
DCD SPI1_IRQHandler ;SPI1 17:
|
||||
DCD ADC0_IRQHandler ;ADC0 ready 18:
|
||||
DCD ADC1_IRQHandler ;ADC1 ready 19:
|
||||
DCD TIM5_IRQHandler ;TIM5 20:
|
||||
DCD UART1_IRQHandler ;UART1 21:
|
||||
DCD TIM6_IRQHandler ;TIM6 22:
|
||||
DCD EEPROM_IRQHandler ;AFE EEPROM prog 23:
|
||||
DCD EXTI10_11_IRQHandler ;EXTI Line 10,11 24:
|
||||
DCD EXTI12_13_IRQHandler ;EXTI Line 12,13 25:
|
||||
DCD LPTIM2_IRQHandler ;LPTIM2 trigger 26:
|
||||
DCD TIM1_IRQHandler ;TIM1 Global 27:
|
||||
DCD TIM2_IRQHandler ;TIM2 Global 28:
|
||||
DCD LPTIM1_IRQHandler ;LPTIM1 trigger 29:
|
||||
DCD MACL_IRQHandler ; MACL RDY,ERR 30:
|
||||
DCD I2C1_EV_IRQHandler ;I2C1 Evnt 31:
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT ADC_ERR_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT CROSSLINK_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_7_IRQHandler [WEAK]
|
||||
EXPORT DMA1_CH0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_CH1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_CH2_3_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT RTCAlarm_IRQHandler [WEAK]
|
||||
EXPORT QSPI_IRQHandlern [WEAK]
|
||||
EXPORT MIO_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT EEPROM_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_11_IRQHandler [WEAK]
|
||||
EXPORT EXTI12_13_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM1_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT MACL_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
|
||||
PVD_IRQHandler
|
||||
ADC_ERR_IRQHandler
|
||||
RTC_IRQHandler
|
||||
CROSSLINK_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_1_IRQHandler
|
||||
EXTI2_3_IRQHandler
|
||||
EXTI4_7_IRQHandler
|
||||
DMA1_CH0_IRQHandler
|
||||
DMA1_CH1_IRQHandler
|
||||
DMA1_CH2_3_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
UART0_IRQHandler
|
||||
RTCAlarm_IRQHandler
|
||||
QSPI_IRQHandlern
|
||||
MIO_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
UART1_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
EEPROM_IRQHandler
|
||||
EXTI10_11_IRQHandler
|
||||
EXTI12_13_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
TIM1_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
MACL_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, =Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, =(Heap_Mem + Heap_Size)
|
||||
LDR R3, =Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
Reference in New Issue
Block a user