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271
startup/KEIL/startup_lh32m0g3x.s
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271
startup/KEIL/startup_lh32m0g3x.s
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;/**************************************************************************//**
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; * @file startup_ARMCM0.s
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; * @brief CMSIS Core Device Startup File for
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; * ARMCM0 Device Series
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; * @version V1.08
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; * @version 23. November 2012
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; *
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; * @note
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; *
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; ******************************************************************************/
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;/* Copyright (c) 2011 - 2012 ARM LIMITED
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;
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; All rights reserved.
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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; - Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; - Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; - Neither the name of ARM nor the names of its contributors may be used
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; to endorse or promote products derived from this software without
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; specific prior written permission.
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; *
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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; ---------------------------------------------------------------------------*/
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;/*
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;*/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000800
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000 ;!!!Make sure if need: 0x00000400
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY ;
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD 0 ; Reserved
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DCD PVD_IRQHandler ; PVD 1:
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DCD ADC_ERR_IRQHandler ;ADC ERROR 2:
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DCD RTC_IRQHandler ; 3: RTC
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DCD CROSSLINK_IRQHandler ;CROSSLINK 4:
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DCD RCC_IRQHandler ; 5: RCC
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DCD EXTI0_1_IRQHandler ;EXTI Line 0,1 6:
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DCD EXTI2_3_IRQHandler ;EXTI Line 2,3 7:
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DCD EXTI4_7_IRQHandler ;EXTI Line 4..7 8:
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DCD DMA1_CH0_IRQHandler ;DMA1_Channel 0 9
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DCD DMA1_CH1_IRQHandler ;DMA1_Channel 1 10:
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DCD DMA1_CH2_3_IRQHandler ;DMA1_Channel 2,3 11:
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DCD SPI0_IRQHandler ;SPI0 12:
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DCD UART0_IRQHandler ;UART0 13:
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DCD RTCAlarm_IRQHandler ;RTCAlarm 14:
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DCD QSPI_IRQHandlern ;QSPI FLASH 15:
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DCD MIO_IRQHandler ;MIO 16:
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DCD SPI1_IRQHandler ;SPI1 17:
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DCD ADC0_IRQHandler ;ADC0 ready 18:
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DCD ADC1_IRQHandler ;ADC1 ready 19:
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DCD TIM5_IRQHandler ;TIM5 20:
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DCD UART1_IRQHandler ;UART1 21:
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DCD TIM6_IRQHandler ;TIM6 22:
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DCD EEPROM_IRQHandler ;AFE EEPROM prog 23:
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DCD EXTI10_11_IRQHandler ;EXTI Line 10,11 24:
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DCD EXTI12_13_IRQHandler ;EXTI Line 12,13 25:
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DCD LPTIM2_IRQHandler ;LPTIM2 trigger 26:
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DCD TIM1_IRQHandler ;TIM1 Global 27:
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DCD TIM2_IRQHandler ;TIM2 Global 28:
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DCD LPTIM1_IRQHandler ;LPTIM1 trigger 29:
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DCD MACL_IRQHandler ; MACL RDY,ERR 30:
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DCD I2C1_EV_IRQHandler ;I2C1 Evnt 31:
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT PVD_IRQHandler [WEAK]
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EXPORT ADC_ERR_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT CROSSLINK_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_1_IRQHandler [WEAK]
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EXPORT EXTI2_3_IRQHandler [WEAK]
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EXPORT EXTI4_7_IRQHandler [WEAK]
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EXPORT DMA1_CH0_IRQHandler [WEAK]
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EXPORT DMA1_CH1_IRQHandler [WEAK]
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EXPORT DMA1_CH2_3_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT RTCAlarm_IRQHandler [WEAK]
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EXPORT QSPI_IRQHandlern [WEAK]
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EXPORT MIO_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT ADC1_IRQHandler [WEAK]
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EXPORT TIM5_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT TIM6_IRQHandler [WEAK]
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EXPORT EEPROM_IRQHandler [WEAK]
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EXPORT EXTI10_11_IRQHandler [WEAK]
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EXPORT EXTI12_13_IRQHandler [WEAK]
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EXPORT LPTIM2_IRQHandler [WEAK]
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EXPORT TIM1_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT LPTIM1_IRQHandler [WEAK]
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EXPORT MACL_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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PVD_IRQHandler
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ADC_ERR_IRQHandler
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RTC_IRQHandler
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CROSSLINK_IRQHandler
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RCC_IRQHandler
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EXTI0_1_IRQHandler
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EXTI2_3_IRQHandler
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EXTI4_7_IRQHandler
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DMA1_CH0_IRQHandler
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DMA1_CH1_IRQHandler
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DMA1_CH2_3_IRQHandler
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SPI0_IRQHandler
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UART0_IRQHandler
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RTCAlarm_IRQHandler
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QSPI_IRQHandlern
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MIO_IRQHandler
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SPI1_IRQHandler
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ADC0_IRQHandler
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ADC1_IRQHandler
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TIM5_IRQHandler
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UART1_IRQHandler
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TIM6_IRQHandler
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EEPROM_IRQHandler
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EXTI10_11_IRQHandler
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EXTI12_13_IRQHandler
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LPTIM2_IRQHandler
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TIM1_IRQHandler
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TIM2_IRQHandler
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LPTIM1_IRQHandler
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MACL_IRQHandler
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I2C1_EV_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, =Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, =(Heap_Mem + Heap_Size)
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LDR R3, =Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END
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