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guishenking
2026-03-20 21:16:58 +08:00
parent 286ff98b8e
commit 90c3d919df
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102
user/MCU/lhl_adc.h Executable file
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#ifndef __LHL_ADC_H__
#define __LHL_ADC_H__
/*==================================================================================*/
//ϵͳ<CFB5><CDB3><EFBFBD>ض<EFBFBD><D8B6><EFBFBD>
/*==================================================================================*/
#define MainADC pADC
//<2F><><EFBFBD><EFBFBD> Gain0 Gain1
#define GAIN1 ADC_PGA_GAIN_1
#define GAIN2 ADC_PGA_GAIN_2
#define GAIN4 ADC_PGA_GAIN_4
#define GAIN8 ADC_PGA_GAIN_8
#define GAIN16 ADC_PGA_GAIN_16
#define GAIN32 ADC_PGA_GAIN_32
#define GAIN64 ADC_PGA_GAIN_64
#define GAIN128 ADC_PGA_GAIN_128
#define GAINPASS ADC_PGA_BYPASS
//<2F><><EFBFBD><EFBFBD> SPS
// //typedef enum {
#define SPS_7813 ADC_SPS_7813 // ADC_SPS_7813 = 0u,
#define SPS_3906 ADC_SPS_3906 // ADC_SPS_3906,
#define SPS_1953 ADC_SPS_1953 // ADC_SPS_1953,
#define SPS_977 ADC_SPS_977 // ADC_SPS_977,
#define SPS_488 ADC_SPS_488 // ADC_SPS_488,
#define SPS_244 ADC_SPS_244 // ADC_SPS_244,
#define SPS_122 ADC_SPS_122 // ADC_SPS_122,
#define SPS_61 ADC_SPS_61 // ADC_SPS_61,
#define SPS_60 ADC_SPS_60 // ADC_SPS_60,
#define SPS_30 ADC_SPS_30 // ADC_SPS_30,
#define SPS_15 ADC_SPS_15 // ADC_SPS_15,
#define SPS_50 ADC_SPS_50 // ADC_SPS_50 = 16u,
#define SPS_25 ADC_SPS_25 // ADC_SPS_25,
#define SPS_12P5 ADC_SPS_12P5 // ADC_SPS_12P5,
#define SPS_10 ADC_SPS_10 // ADC_SPS_10 = 24u,
#define SPS_5 ADC_SPS_5 // ADC_SPS_5,
#define SPS_2P5 ADC_SPS_2P5 // ADC_SPS_2P5,
// //} ADC_DATA_RATE_t;
//<2F><><EFBFBD><EFBFBD> PChan0 NChan0
// typedef enum { typedef enum {
#define ADC0_AIN0 ADC0_AINP_AIN0 // ADC0_AINP_AIN0 = 0x00u, ADC0_AINM_AIN0 = 0x00u,
#define ADC0_AIN1 ADC0_AINP_AIN1 // ADC0_AINP_AIN1, ADC0_AINM_AIN1,
#define ADC0_AIN2 ADC0_AINP_AIN2 // ADC0_AINP_AIN2, ADC0_AINM_AIN2,
#define ADC0_AIN3 ADC0_AINP_AIN3 // ADC0_AINP_AIN3, ADC0_AINM_AIN3,
#define ADC0_AIN4 ADC0_AINP_AIN4 // ADC0_AINP_AIN4, ADC0_AINM_AIN4,
#define ADC0_AIN5 ADC0_AINP_AIN5 // ADC0_AINP_AIN5, ADC0_AINM_AIN5,
#define ADC0_AIN6 ADC0_AINP_AIN6 // ADC0_AINP_AIN6, ADC0_AINM_AIN6,
#define ADC0_AIN7 ADC0_AINP_AIN7 // ADC0_AINP_AIN7, ADC0_AINM_AIN7,
#define ADC0_AIN8 ADC0_AINP_AIN8 // ADC0_AINP_AIN8, ADC0_AINM_AIN8,
#define ADC0_AIN9 ADC0_AINP_AIN9 // ADC0_AINP_AIN9, ADC0_AINM_AIN9,
#define ADC0_AIN10 ADC0_AINP_AIN10 // ADC0_AINP_AIN10, ADC0_AINM_AIN10,
#define ADC0_AIN11 ADC0_AINP_AIN11 // ADC0_AINP_AIN11, ADC0_AINM_AIN11,
#define ADC0_AVSS ADC0_AINP_AVSS // ADC0_AINP_AVSS = 0x10u, ADC0_AINM_AVSS = 0x10u,
#define ADC0_REFP ADC0_AINP_REFP // ADC0_AINP_REFP, ADC0_AINM_REFP,
#define ADC0_CALIBP ADC0_AINP_CALIBP // ADC0_AINP_CALIBP, ADC0_AINM_CALIBN,
// } ADC0_AINP_CHANNEL_t; } ADC0_AINM_CHANNEL_t;
//<2F><><EFBFBD><EFBFBD> PChan1 NChan1
//typedef enum { typedef enum {
#define ADC1_AIN0 ADC1_AINP_AIN0 // ADC1_AINP_AIN0 = 0x00u, ADC1_AINM_AIN0 = 0x00u,
#define ADC1_AIN1 ADC1_AINP_AIN1 // ADC1_AINP_AIN1, ADC1_AINM_AIN1,
#define ADC1_AIN2 ADC1_AINP_AIN2 // ADC1_AINP_AIN2, ADC1_AINM_AIN2,
#define ADC1_AIN3 ADC1_AINP_AIN3 // ADC1_AINP_AIN3, ADC1_AINM_AIN3,
#define ADC1_AIN4 ADC1_AINP_AIN4 // ADC1_AINP_AIN4, ADC1_AINM_AIN4,
#define ADC1_AIN5 ADC1_AINP_AIN5 // ADC1_AINP_AIN5, ADC1_AINM_AIN5,
#define ADC1_AIN6 ADC1_AINP_AIN6 // ADC1_AINP_AIN6, ADC1_AINM_AIN6,
#define ADC1_AIN7 ADC1_AINP_AIN7 // ADC1_AINP_AIN7, ADC1_AINM_AIN7,
#define ADC1_AIN8 ADC1_AINP_AIN8 // ADC1_AINP_AIN8, ADC1_AINM_AIN8,
#define ADC1_AIN9 ADC1_AINP_AIN9 // ADC1_AINP_AIN9, ADC1_AINM_AIN9,
#define ADC1_AIN10 ADC1_AINP_AIN10 // ADC1_AINP_AIN10, ADC1_AINM_AIN10,
#define ADC1_AIN11 ADC1_AINP_AIN11 // ADC1_AINP_AIN11, ADC1_AINM_AIN11,
#define ADC1_AINTEMPP ADC1_AINP_TEMPP // ADC1_AINP_TEMPP = 0x10u, ADC1_AINM_TEMPN = 0x10u,
#define ADC1_AVSS ADC1_AINP_AVSS // ADC1_AINP_AVSS, ADC1_AINM_AVSS,
#define ADC1_REFP ADC1_AINP_REFP // ADC1_AINP_REFP, ADC1_AINM_REFP,
#define ADC1_DACP ADC1_AINP_DACP // ADC1_AINP_DACP, ADC1_AINM_DACN,
#define ADC1_LOOPP ADC1_AINP_LOOPP // ADC1_AINP_LOOPP, ADC1_AINM_LOOPN,
#define ADC1_AVDDP ADC1_AINP_AVDDP // ADC1_AINP_AVDDP, ADC1_AINM_AVDDN,
#define ADC1_IOVDDP ADC1_AINP_IOVDDP // ADC1_AINP_IOVDDP, ADC1_AINM_IOVDDN,
#define ADC1_CALIBP ADC1_AINP_CALIBP // ADC1_AINP_CALIBP, ADC1_AINM_CALIBN,
//} ADC1_AINP_CHANNEL_t; } ADC1_AINM_CHANNEL_t;
/*==================================================================================*/
//ϵͳ<CFB5><CDB3><EFBFBD><EFBFBD>
/*==================================================================================*/
void ADC_REF_Init(u8 vref,u8 vdrive);
void ADC_Init(ADC_ID_t ADCx ,u8 SPS ,u8 Gain, u8 PChan, u8 NChan );
void ADC_SyncCmd(FunctionalState NewState);
void StartADC(ADC_ID_t ADCx);
void StopADC(ADC_ID_t ADCx);
uint32_t ADC_ReadData(ADC_ID_t ADCx);
void ADC_Init_For_SNOOZE(ADC_ID_t ADCx ,u8 SPS ,u8 Gain, u8 PChan, u8 NChan );
void ADC_Init_For_LowerPower(ADC_ID_t ADCx, u8 SPS, u8 Gain, u8 PChan, u8 NChan);
//ADC<44>жϻص<CFBB>
typedef void (*adc_irq_callback_t)(void);
void ADC_register_irq_callback(ADC_ID_t ADCx, adc_irq_callback_t tim_irq_callback);
#endif