/****************************************************************************** * 版权所有：苏州领慧立芯科技有限公司 * Copyright (c) 2020-2025 Suzhou Legendsemi Technology Co., Ltd. ****************************************************************************** * All rights reserved. Distributed under MIT license. * The file is encoded in UTF-8 without signature. * @file lh32m0g30x_timer.h * @version 2025-09-25 ******************************************************************************/ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __LH32M0G3x_TIM_H #define __LH32M0G3x_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "lh32m0xx_lhl.h" /* Definition ----------------------------------------------------------------*/ /** * @brief TIM_Counter_Mode */ typedef enum { TIM_COUNTERMODE_UP = ((uint16_t)0x0000), TIM_COUNTERMODE_DOWN = ((uint16_t)0x0010), TIM_COUNTERMODE_CENTERALIGNED1 = ((uint16_t)0x0020), TIM_COUNTERMODE_CENTERALIGNED2 = ((uint16_t)0x0040), TIM_COUNTERMODE_CENTERALIGNED3 = ((uint16_t)0x0060), } TIM_COUNTERMODE_t; /** * @brief TIM_Clock_Division_CKD */ typedef enum { TIM_CKD_DIV1 = ((uint16_t)0x0000), TIM_CKD_DIV2 = ((uint16_t)0x0100), TIM_CKD_DIV4 = ((uint16_t)0x0200), } TIM_CKD_DIV_t; /** * @brief TIM_interrupt_sources */ #define TIM_IT_UPDATE ((uint16_t)0x0001) #define TIM_IT_CC1 ((uint16_t)0x0002) #define TIM_IT_CC2 ((uint16_t)0x0004) #define TIM_IT_TRIGGER ((uint16_t)0x0040) /** * @brief TIM_Flags */ typedef enum { TIM_FLAG_UIF = ((uint16_t)0x0001), TIM_FLAG_CC1IF = ((uint16_t)0x0002), TIM_FLAG_CC2IF = ((uint16_t)0x0004), TIM_FLAG_TIF = ((uint16_t)0x0040), TIM_FLAG_CC1OF = ((uint16_t)0x0200), TIM_FLAG_CC2OF = ((uint16_t)0x0400), } TIM_FLAG_t; /** @defgroup TIM_Channel * @{ */ typedef enum { TIM_CHANNEL_1 = ((uint16_t)0x0000), TIM_CHANNEL_2 = ((uint16_t)0x0004), } TIM_CHANNEL_t; /** @defgroup TIM_Input_Capture_Polarity * @{ */ typedef enum { TIM_ICPOLARITY_RISING = ((uint16_t)0x0000), TIM_ICPOLARITY_FALLING = ((uint16_t)0x0002), TIM_ICPOLARITY_BOTHEDGE = ((uint16_t)0x000A), } TIM_ICPOLARITY_t; /** @defgroup TIM_Input_Capture_Selection * @{ */ typedef enum { TIM_ICSELECTION_DIRECTTI = ((uint16_t)0x0001), /*!< TIM Input 1 or 2 is selected to be connected to IC1 or IC2, respectively */ TIM_ICSELECTION_INDIRECTTI = ((uint16_t)0x0002), /*!< TIM Input 1 or 2 is selected to be connected to IC2 or IC1, respectively. */ TIM_ICSELECTION_TRC = ((uint16_t)0x0003), /*!< TIM Input 1 or 2 is selected to be connected to TRC. */ } TIM_ICSELECTION_t; /** @defgroup TIM_Input_Capture_Prescaler * @{ */ typedef enum { TIM_ICPSC_DIV1 = ((uint16_t)0x0000), /*!< Capture performed each time an edge is detected on the capture input. */ TIM_ICPSC_DIV2 = ((uint16_t)0x0004), /*!< Capture performed once every 2 events. */ TIM_ICPSC_DIV4 = ((uint16_t)0x0008), /*!< Capture performed once every 4 events. */ TIM_ICPSC_DIV8 = ((uint16_t)0x000C), /*!< Capture performed once every 8 events. */ } TIM_ICPRESCALER_t; /** @defgroup TIM_Event_Source * @{ */ typedef enum { TIM_EVENTSRC_UPDATE = ((uint16_t)0x0001), TIM_EVENTSRC_CC1 = ((uint16_t)0x0002), TIM_EVENTSRC_CC2 = ((uint16_t)0x0004), TIM_EVENTSRC_TRIGGER = ((uint16_t)0x0040), } TIM_EVENTSOURCE_t; /** @defgroup TIM_Output_Compare_modes * @{ */ typedef enum { TIM_OCMODE_TIMING = ((uint16_t)0x0000), TIM_OCMODE_ACTIVE = ((uint16_t)0x0010), TIM_OCMODE_INACTIVE = ((uint16_t)0x0020), TIM_OCMODE_TOGGLE = ((uint16_t)0x0030), TIM_OCMODE_FORCED_INACTIVE = ((uint16_t)0x0040), TIM_OCMODE_FORCED_ACTIVE = ((uint16_t)0x0050), } TIM_OCMODE_t; /** @defgroup TIM_Output_PWM_modes * @{ */ typedef enum { TIM_PWMMODE_PWM1 = ((uint16_t)0x0060), TIM_PWMMODE_PWM2 = ((uint16_t)0x0070), } TIM_PWMMODE_t; /** @defgroup TIM_Output_Compare_state * @{ */ #define TIM_OutputState_Disable ((uint16_t)0x0000) #define TIM_OutputState_Enable ((uint16_t)0x0001) /** @defgroup TIM_Output_Compare_Polarity * @{ */ typedef enum { TIM_OCPOLARITY_ACTIVE_HIGH = ((uint16_t)0x0000), TIM_OCPOLARITY_ACTIVE_LOW = ((uint16_t)0x0002), } TIM_OCPOLARITY_t; /** @defgroup TIM_Output_PWM_Polarity * @{ */ typedef enum { TIM_PWMPOLARITY_ACTIVE_HIGH = ((uint16_t)0x0000), TIM_PWMPOLARITY_ACTIVE_LOW = ((uint16_t)0x0002), } TIM_PWMPOLARITY_t; typedef enum { TIM_URS_ALL = 0u, TIM_URS_OVERFLOW, } TIM_URS_t; /** @defgroup TIM_Internal_Trigger_Selection * @{ */ typedef enum { TIM_TS_DISABLED = ((uint16_t)0x0000), TIM_TS_ITR0 = ((uint16_t)0x0000), TIM_TS_ITR1 = ((uint16_t)0x0010), TIM_TS_ITR2 = ((uint16_t)0x0020), TIM_TS_ITR3 = ((uint16_t)0x0030), TIM_TS_TI1F_ED = ((uint16_t)0x0040), TIM_TS_TI1FP1 = ((uint16_t)0x0050), TIM_TS_TI2FP2 = ((uint16_t)0x0060), TIM_TS_ETRF = ((uint16_t)0x0070), } TIM_TS_t; /** @defgroup TIM_Slave_Mode * @{ */ typedef enum { TIM_SLAVEMODE_DISABLED = 0x0u, TIM_SLAVEMODE_ENCODER1 = 0x1u, TIM_SLAVEMODE_ENCODER2 = 0x2u, TIM_SLAVEMODE_ENCODER3 = 0x3u, TIM_SLAVEMODE_RESET = 0x4u, TIM_SLAVEMODE_GATED = 0x5u, TIM_SLAVEMODE_TRIGGER = 0x6u, TIM_SLAVEMODE_EXTERNAL1 = 0x7u, // TIM_SLAVEMODE_EXTERNAL2 = 0x8u, } TIM_SLAVEMODE_t; typedef enum { TIM_ETF_DISABLE = 0x00U, /*!< No filter */ TIM_ETF_FCK_N2 = 0x01U, /*!< fSAMPLING = fCK_INT, N=2 */ TIM_ETF_FCK_N4 = 0x02U, /*!< fSAMPLING = fCK_INT, N=4 */ TIM_ETF_FCK_N8 = 0x03U, TIM_ETF_FDTS_D2_N6 = 0x04U, /*!< fSAMPLING = fDTS/2, N=6 */ TIM_ETF_FDTS_D2_N8 = 0x05U, TIM_ETF_FDTS_D4_N6 = 0x06U, TIM_ETF_FDTS_D4_N8 = 0x07U, TIM_ETF_FDTS_D8_N6 = 0x08U, TIM_ETF_FDTS_D8_N8 = 0x09U, TIM_ETF_FDTS_D16_N5 = 0x0AU, TIM_ETF_FDTS_D16_N6 = 0x0BU, TIM_ETF_FDTS_D16_N8 = 0x0CU, TIM_ETF_FDTS_D32_N5 = 0x0DU, TIM_ETF_FDTS_D32_N6 = 0x0EU, TIM_ETF_FDTS_D32_N8 = 0x0FU, /*!< fSAMPLING = fDTS/32, N=8 */ } TIM_ETF_t; /** * @brief External Trigger Prescaler */ typedef enum { TIM_ETR_PRESCALER_DISABLE = 0x00U, /*!< Prescaler off */ TIM_ETR_PRESCALER_DIV2 = 0x01U, /*!< ETRP frequency divided by 2 */ TIM_ETR_PRESCALER_DIV4 = 0x02U, /*!< ETRP frequency divided by 4 */ TIM_ETR_PRESCALER_DIV8 = 0x03U /*!< ETRP frequency divided by 8 */ } TIM_ETPSC_t; /** * @brief External Trigger Polarity */ typedef enum { TIM_ETR_POLARITY_NONINVERTED = 0x00U, /*!< ETR non-inverted, active high/rising */ TIM_ETR_POLARITY_INVERTED = 0x01U /*!< ETR inverted, active low/falling */ } TIM_ETPOL_t; /** * @brief TIM Time Base Init structure definition */ typedef struct { uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between 0x0000 and 0xFFFF */ uint16_t Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between 0x0000 and 0xFFFF */ TIM_COUNTERMODE_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ FunctionalState AutoReloadPreload; /*!< Specifies if ARR Preload or Immediate Load */ TIM_CKD_DIV_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_Clock_Division_CKD */ } TIM_InitTypeDef; /** * @brief TIM Output Compare Init structure definition */ typedef struct { TIM_OCMODE_t OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_modes */ TIM_OCPOLARITY_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ FunctionalState OCPinState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_Output_Compare_state */ FunctionalState OCPreload; /*!< 禁用或使能CCR1预装载功能 */ uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between 0x0000 and 0xFFFF */ } TIM_OCInitTypeDef; /** * @brief TIM PWM Init structure definition */ typedef struct { TIM_PWMMODE_t PWMMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_modes */ TIM_PWMPOLARITY_t PWMPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ FunctionalState PWMFastMode; /*!< 禁用或使能CCR1 PWM模式下快速装载功能 */ FunctionalState PWMPreload; /*!< 禁用或使能CCR1 PWM预装载功能 */ uint16_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between 0x0000 and 0xFFFF */ } TIM_PWMInitTypeDef; /** * @brief TIM Input Capture Init structure definition */ typedef struct { uint16_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between 0x0 and 0xF */ TIM_ICPRESCALER_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ TIM_ICPOLARITY_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ TIM_ICSELECTION_t ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint8_t Reserved; } TIM_ICInitTypeDef; /** * @brief Slave Mode Configuration Structure */ typedef struct { /* Basic Configuration */ TIM_SLAVEMODE_t SlaveMode; /*!< Slave mode selection */ TIM_TS_t TriggerSource; /*!< Trigger source selection */ FunctionalState MasterSlaveSync; /*!< Master/Slave synchronization */ /* External Trigger Configuration (only when triggerSource = TIM_TS_ETRF) */ TIM_ETPOL_t ETRPolarity; /*!< ETR polarity */ TIM_ETPSC_t ETRPrescaler; /*!< ETR prescaler */ TIM_ETF_t ETRFilter; /*!< ETR digital filter */ } TIM_SlaveModeInitTypeDef; /** @defgroup TIM_One_Pulse_Mode * @{ */ #define TIM_OPMode_Single ((uint16_t)0x0008) #define TIM_OPMode_Repetitive ((uint16_t)0x0000) #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ ((MODE) == TIM_OPMode_Repetitive)) /** * @} */ /** * @} */ /** @defgroup TIM_Capture_Compare_state * @{ */ #define TIM_CCx_Enable ((uint16_t)0x0001) #define TIM_CCx_Disable ((uint16_t)0x0000) #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ ((CCX) == TIM_CCx_Disable)) /** * @} */ /** @defgroup TIM_AOE_Bit_Set_Reset * @{ */ #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ ((STATE) == TIM_AutomaticOutput_Disable)) /** * @} */ /** @defgroup Lock_level * @{ */ #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) #define TIM_LOCKLevel_1 ((uint16_t)0x0100) #define TIM_LOCKLevel_2 ((uint16_t)0x0200) #define TIM_LOCKLevel_3 ((uint16_t)0x0300) #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ ((LEVEL) == TIM_LOCKLevel_1) || \ ((LEVEL) == TIM_LOCKLevel_2) || \ ((LEVEL) == TIM_LOCKLevel_3)) /** * @} */ /** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state * @{ */ #define TIM_OSSIState_Enable ((uint16_t)0x0400) #define TIM_OSSIState_Disable ((uint16_t)0x0000) #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ ((STATE) == TIM_OSSIState_Disable)) /** * @} */ /** @defgroup OSSR_Off_State_Selection_for_Run_mode_state * @{ */ #define TIM_OSSRState_Enable ((uint16_t)0x0800) #define TIM_OSSRState_Disable ((uint16_t)0x0000) #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ ((STATE) == TIM_OSSRState_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Idle_State * @{ */ #define TIM_OCIdleState_Set ((uint16_t)0x0100) #define TIM_OCIdleState_Reset ((uint16_t)0x0000) #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ ((STATE) == TIM_OCIdleState_Reset)) /** * @} */ /** @defgroup TIM_DMA_Base_address * @{ */ #define TIM_DMABase_CR1 ((uint16_t)0x0000) #define TIM_DMABase_CR2 ((uint16_t)0x0001) #define TIM_DMABase_SMCR ((uint16_t)0x0002) #define TIM_DMABase_DIER ((uint16_t)0x0003) #define TIM_DMABase_SR ((uint16_t)0x0004) #define TIM_DMABase_EGR ((uint16_t)0x0005) #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) #define TIM_DMABase_CCER ((uint16_t)0x0008) #define TIM_DMABase_CNT ((uint16_t)0x0009) #define TIM_DMABase_PSC ((uint16_t)0x000A) #define TIM_DMABase_ARR ((uint16_t)0x000B) #define TIM_DMABase_RCR ((uint16_t)0x000C) #define TIM_DMABase_CCR1 ((uint16_t)0x000D) #define TIM_DMABase_CCR2 ((uint16_t)0x000E) #define TIM_DMABase_CCR3 ((uint16_t)0x000F) #define TIM_DMABase_CCR4 ((uint16_t)0x0010) #define TIM_DMABase_BDTR ((uint16_t)0x0011) #define TIM_DMABase_DCR ((uint16_t)0x0012) #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ ((BASE) == TIM_DMABase_CR2) || \ ((BASE) == TIM_DMABase_SMCR) || \ ((BASE) == TIM_DMABase_DIER) || \ ((BASE) == TIM_DMABase_SR) || \ ((BASE) == TIM_DMABase_EGR) || \ ((BASE) == TIM_DMABase_CCMR1) || \ ((BASE) == TIM_DMABase_CCMR2) || \ ((BASE) == TIM_DMABase_CCER) || \ ((BASE) == TIM_DMABase_CNT) || \ ((BASE) == TIM_DMABase_PSC) || \ ((BASE) == TIM_DMABase_ARR) || \ ((BASE) == TIM_DMABase_RCR) || \ ((BASE) == TIM_DMABase_CCR1) || \ ((BASE) == TIM_DMABase_CCR2) || \ ((BASE) == TIM_DMABase_CCR3) || \ ((BASE) == TIM_DMABase_CCR4) || \ ((BASE) == TIM_DMABase_BDTR) || \ ((BASE) == TIM_DMABase_DCR)) /** * @} */ /** @defgroup TIM_DMA_Burst_Length * @{ */ #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ ((LENGTH) == TIM_DMABurstLength_18Transfers)) /** * @} */ /** @defgroup TIM_DMA_sources * @{ */ #define TIM_DMA_Update ((uint16_t)0x0100) #define TIM_DMA_CC1 ((uint16_t)0x0200) #define TIM_DMA_CC2 ((uint16_t)0x0400) #define TIM_DMA_CC3 ((uint16_t)0x0800) #define TIM_DMA_CC4 ((uint16_t)0x1000) #define TIM_DMA_COM ((uint16_t)0x2000) #define TIM_DMA_Trigger ((uint16_t)0x4000) #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) /** * @} */ /** @defgroup TIM_External_Trigger_Prescaler * @{ */ #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) /** * @} */ /** @defgroup TIM_TIx_External_Clock_Source * @{ */ #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) /** * @} */ /** @defgroup TIM_External_Trigger_Polarity * @{ */ #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) /** * @} */ /** @defgroup TIM_Prescaler_Reload_Mode * @{ */ #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ ((RELOAD) == TIM_PSCReloadMode_Immediate)) /** * @} */ /** @defgroup TIM_Forced_Action * @{ */ #define TIM_ForcedAction_Active ((uint16_t)0x0050) #define TIM_ForcedAction_InActive ((uint16_t)0x0040) #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ ((ACTION) == TIM_ForcedAction_InActive)) /** * @} */ /** @defgroup TIM_Encoder_Mode * @{ */ #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ ((MODE) == TIM_EncoderMode_TI2) || \ ((MODE) == TIM_EncoderMode_TI12)) /** * @} */ #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) /** * @} */ /** @defgroup TIM_Update_Source * @{ */ #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller. */ #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ ((SOURCE) == TIM_UpdateSource_Regular)) /** * @} */ /** @defgroup TIM_Output_Compare_Preload_State * @{ */ #define TIM_OCPreload_Enable ((uint16_t)0x0008) #define TIM_OCPreload_Disable ((uint16_t)0x0000) #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ ((STATE) == TIM_OCPreload_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Fast_State * @{ */ #define TIM_OCFast_Enable ((uint16_t)0x0004) #define TIM_OCFast_Disable ((uint16_t)0x0000) #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ ((STATE) == TIM_OCFast_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Clear_State * @{ */ #define TIM_OCClear_Enable ((uint16_t)0x0080) #define TIM_OCClear_Disable ((uint16_t)0x0000) #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ ((STATE) == TIM_OCClear_Disable)) /** * @} */ /** @defgroup TIM_Trigger_Output_Source * @{ */ #define TIM_TRGOSource_Reset ((uint16_t)0x0000) #define TIM_TRGOSource_Enable ((uint16_t)0x0010) #define TIM_TRGOSource_Update ((uint16_t)0x0020) #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ ((SOURCE) == TIM_TRGOSource_Enable) || \ ((SOURCE) == TIM_TRGOSource_Update) || \ ((SOURCE) == TIM_TRGOSource_OC1) || \ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ ((SOURCE) == TIM_TRGOSource_OC4Ref)) /** @defgroup TIM_Master_Slave_Mode * @{ */ #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ ((STATE) == TIM_MasterSlaveMode_Disable)) /** * @} */ #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) /** * @} */ /** @defgroup TIM_Input_Capture_Filer_Value * @{ */ #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} */ /** @defgroup TIM_External_Trigger_Filter * @{ */ #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) /** * @} */ /** @defgroup TIM_Legacy * @{ */ #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers /** * @} */ /** * @} */ /** @defgroup TIM_Exported_Macros * @{ */ /** * @} */ /** @defgroup TIM_Exported_Functions * @{ */ //void TIM_DeInit(TIM_TypeDef* TIMx); //void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_TimeBaseInitStruct); //void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); //void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); //void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); //void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); //void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); //void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); //void TIM_TimeBaseStructInit(TIM_InitTypeDef* TIM_TimeBaseInitStruct); //void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); //void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); //void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); //void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); //void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); //void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); //void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); //void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); //void TIM_InternalClockConfig(TIM_TypeDef* TIMx); //void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); //void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, // uint16_t TIM_ICPolarity, uint16_t ICFilter); //void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, // uint16_t ExtTRGFilter); //void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, // uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); //void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, // uint16_t ExtTRGFilter); //void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); //void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); //void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); //void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, // uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); //void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); //void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); //void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); //void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); //void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); //void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); //void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); //void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); //void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); //void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); //void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); //void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); //void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); //void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); //void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); //void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); //void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); //void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); //void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); //void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); //void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); //void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); //void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); //void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); //void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); //void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); //void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); //void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); //void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); //void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); //void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); //void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); //void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); //void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); //void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); //void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); //void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); //void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); //void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); //void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); //void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); //void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); //void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); //void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); //void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); //void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); //void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); //void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); //uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); //uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); //uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); //uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); //uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); //uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); /* Function Declaration ------------------------------------------------------*/ void LHL_TIM_DeInit(TIM_TypeDef* TIMx); void LHL_TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct); void LHL_TIM_Start(TIM_TypeDef* TIMx); void LHL_TIM_Stop(TIM_TypeDef* TIMx); void LHL_TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITs, FunctionalState NewState); ITStatus LHL_TIM_GetPending(TIM_TypeDef* TIMx, uint16_t TIM_IT); void LHL_TIM_ClearPending(TIM_TypeDef* TIMx, uint16_t TIM_IT); FlagStatus LHL_TIM_GetFlag(TIM_TypeDef* TIMx, TIM_FLAG_t TIM_FLAG); void LHL_TIM_ClearFlag(TIM_TypeDef* TIMx, TIM_FLAG_t TIM_FLAG); void LHL_TIM_IC_Init(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct, TIM_CHANNEL_t TIM_CHx); void LHL_TIM_IC_Cmd(TIM_TypeDef* TIMx, TIM_CHANNEL_t TIM_CHx, FunctionalState NewState); void LHL_TIM_IC_SetPrescaler(TIM_TypeDef* TIMx, TIM_ICPRESCALER_t TIM_ICPSC, TIM_CHANNEL_t TIM_CHx); void LHL_TIM_IC_Start(TIM_TypeDef* TIMx, TIM_CHANNEL_t TIM_CHx); void LHL_TIM_IC_Stop(TIM_TypeDef* TIMx, TIM_CHANNEL_t TIM_CHx); uint16_t LHL_TIM_IC_GetCapture(TIM_TypeDef* TIMx, TIM_CHANNEL_t TIM_CHx); void LHL_TIM_OC_Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct, TIM_CHANNEL_t TIM_CHx); void LHL_TIM_OC_Cmd(TIM_TypeDef* TIMx, TIM_CHANNEL_t TIM_CHx, FunctionalState NewState); void LHL_TIM_OC_SetCompare(TIM_TypeDef* TIMx, TIM_CHANNEL_t TIM_CHx, uint16_t Compare); void LHL_TIM_OC_Start(TIM_TypeDef* TIMx, TIM_CHANNEL_t TIM_CHx); void LHL_TIM_OC_Stop(TIM_TypeDef* TIMx, TIM_CHANNEL_t TIM_CHx); LHL_StatusTypeDef LHL_TIM_SMInit(TIM_TypeDef* TIMx, TIM_SlaveModeInitTypeDef *smInit); void LHL_TIM_PWM_Init(TIM_TypeDef* TIMx, TIM_PWMInitTypeDef* TIM_PWMInitStruct, TIM_CHANNEL_t TIM_CHx); void LHL_TIM_PWM_SetDutyCycle(TIM_TypeDef* TIMx, uint16_t DutyCyle, TIM_CHANNEL_t TIM_CHx); void LHL_TIM_GenerateEvent(TIM_TypeDef* TIMx, TIM_EVENTSOURCE_t TIM_EventSource); void LHL_TIM_SetOnePulseMode(TIM_TypeDef* TIMx, FunctionalState NewState); void LHL_TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); void LHL_TIM_SetSlaveMode(TIM_TypeDef* TIMx, TIM_SLAVEMODE_t TIM_SlaveMode); void LHL_TIM_SetInputTrigger(TIM_TypeDef* TIMx, TIM_TS_t TIM_InputTriggerSource); #ifdef __cplusplus } #endif #endif /*********************************End of File**********************************/