215 lines
8.6 KiB
C
215 lines
8.6 KiB
C
/******************************************************************************
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* 版权所有：苏州领慧立芯科技有限公司
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* Copyright (c) 2020-2025 Suzhou Legendsemi Technology Co., Ltd.
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******************************************************************************
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* All rights reserved. Distributed under MIT license.
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* The file is encoded in UTF-8 without signature.
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* @file lh32m0g30x_rcc.h
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* @version 2025-09-01
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******************************************************************************/
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/* Define to prevent recursive inclusion ------------------------------------*/
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#ifndef __LH32M0G3x_RCC_H
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#define __LH32M0G3x_RCC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "lh32m0xx_lhl.h"
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/* Public Definition ---------------------------------------------------------*/
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/**
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* @brief 获取RCC时钟树结构体参数
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*/
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typedef struct
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{
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uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
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uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
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uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
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uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
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} RCC_ClocksTypeDef;
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/**
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* @brief RCC System, AHB and APB bus clock configuration structure definition
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*/
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typedef struct
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{
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uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
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This parameter can be a value of @ref RCC_System_Clock_Source */
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uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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This parameter can be a value of @ref RCC_HCLK_Clock_Source */
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uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_APB1_Clock_Source */
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uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_APB1_Clock_Source */
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} RCC_ClockInitTypeDef;
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/**
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* @brief RCC Reset Source Type Define Structure
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*/
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typedef struct
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{
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FlagStatus PORReset; /*!< POR/PDR reset flag */
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FlagStatus PINReset; /*!< NRST pin reset flag */
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FlagStatus SFTReset; /*!< Software reset flag */
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FlagStatus IWDGReset; /*!< Independent watchdog reset flag */
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} RCC_ResetSourceTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup RCC_System_Clock_Source
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* @{
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*/
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#define RCC_SYSCLK_SRC_HSI_DIV2 ((uint32_t)0x4)
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#define RCC_SYSCLK_SRC_HSI_DIV1 ((uint32_t)0x0)
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#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x1)
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#define RCC_SYSCLK_SRC_LSI ((uint32_t)0x2)
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#define RCC_SYSCLK_SRC_LSE ((uint32_t)0x3)
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/** @defgroup RCC_HSE_configuration
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* @{
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*/
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#define RCC_HSE_OFF (0)
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#define RCC_HSE_ON (RCC_CR_HSEON_Msk)
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/** @defgroup RCC_Flag
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* @{
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*/
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#define RCC_FLAG_LSIRDY (RCC_CSR_LSIRDY_Msk)
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#define RCC_FLAG_PVDRST (RCC_CSR_PVDRSTF_Msk)
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#define RCC_FLAG_PINRST (RCC_CSR_PINRSTF_Msk)
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#define RCC_FLAG_PORRST (RCC_CSR_PORRSTF_Msk)
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#define RCC_FLAG_SFTRST (RCC_CSR_SFTRSTF_Msk)
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#define RCC_FLAG_IWDGRST (RCC_CSR_IWDGRSTF_Msk)
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/** @defgroup HSI DIV
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* @{
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*/
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#define RCC_HSI_DIV1 ((uint32_t)0x0)
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#define RCC_HSI_DIV2 ((uint32_t)0x1)
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/** @defgroup RCC_SYSCLK_Source
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* @{
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*/
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#define RCC_SW_HSI ((uint32_t)0x0)
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#define RCC_SW_HSE ((uint32_t)0x1)
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#define RCC_SW_LSI ((uint32_t)0x2)
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#define RCC_SW_LSE ((uint32_t)0x3)
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/** @defgroup RCC_AHB_Clock_Source
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* @{
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*/
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#define RCC_SYSCLK_DIV1 ((uint32_t)0x0)
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#define RCC_SYSCLK_DIV2 ((uint32_t)0x8)
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#define RCC_SYSCLK_DIV4 ((uint32_t)0x9)
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#define RCC_SYSCLK_DIV8 ((uint32_t)0xA)
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#define RCC_SYSCLK_DIV16 ((uint32_t)0xB)
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#define RCC_SYSCLK_DIV64 ((uint32_t)0xC)
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#define RCC_SYSCLK_DIV128 ((uint32_t)0xD)
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#define RCC_SYSCLK_DIV256 ((uint32_t)0xE)
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#define RCC_SYSCLK_DIV512 ((uint32_t)0xF)
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/** @defgroup RCC_APB1_APB2_Clock_Source
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* @{
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*/
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#define RCC_HCLK_DIV1 ((uint32_t)0x0)
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#define RCC_HCLK_DIV2 ((uint32_t)0x4)
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#define RCC_HCLK_DIV4 ((uint32_t)0x5)
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#define RCC_HCLK_DIV8 ((uint32_t)0x6)
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#define RCC_HCLK_DIV16 ((uint32_t)0x7)
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/** @defgroup RCC_MCO_Clock_Source
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* @{
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*/
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#define RCC_MCOSOURCE_LSI ((uint32_t)0)
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#define RCC_MCOSOURCE_SYSCLK ((uint32_t)1)
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#define RCC_MCOSOURCE_HSI ((uint32_t)2)
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#define RCC_MCOSOURCE_HSE ((uint32_t)3)
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#define RCC_MCOSOURCE_LSE ((uint32_t)4)
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#define RCC_MCOSOURCE_PCLK1 ((uint32_t)5)
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#define RCC_MCOSOURCE_PCLK2 ((uint32_t)6)
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#define RCC_MCOSOURCE_HCLK ((uint32_t)7)
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#define RCC_MCOSOURCE_ADC_OUT_CLK ((uint32_t)8)
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/** @defgroup RTC_clock_source
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* @{
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*/
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#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
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#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
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#define RCC_RTCCLKSource_HSE_DIV128 ((uint32_t)0x00000300)
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/* Function used to set the RCC clock configuration to the default reset state */
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void LHL_RCC_DeInit(void);
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LHL_StatusTypeDef LHL_RCC_ClockConfig(const RCC_ClockInitTypeDef *RCC_Clock_Init, uint32_t timeout);
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/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
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LHL_StatusTypeDef LHL_RCC_LSEConfig(FunctionalState NewState);
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LHL_StatusTypeDef LHL_RCC_HSEConfig(FunctionalState NewState);
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void LHL_RCC_HSIConfig(uint32_t RCC_HSI_DIV);
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void LHL_RCC_HSICmd(FunctionalState NewState);
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void LHL_RCC_MCOConfig(uint32_t RCC_MCOSource);
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/* System, AHB and APB busses clocks configuration functions ******************/
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void LHL_RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
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void LHL_RCC_HSIConfig(uint32_t RCC_HSI_DIV);
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void LHL_RCC_HCLKConfig(uint32_t RCC_SYSCLK);
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void LHL_RCC_PCLK1Config(uint32_t RCC_HCLK);
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void LHL_RCC_PCLK2Config(uint32_t RCC_HCLK);
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void LHL_RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
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uint32_t LHL_RCC_GetSystemClockFreq(void);
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uint32_t LHL_RCC_GetHCLKFreq(void);
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uint32_t LHL_RCC_GetPCLK1Freq(void);
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uint32_t LHL_RCC_GetPCLK2Freq(void);
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/* Peripheral clocks configuration functions **********************************/
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void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
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void RCC_RTCCLKCmd(FunctionalState NewState);
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void RCC_BackupResetCmd(FunctionalState NewState);
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void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
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void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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/* Interrupts and flags management functions **********************************/
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FlagStatus LHL_RCC_GetFlag(uint32_t RCC_FLAG);
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void LHL_RCC_ClearFlag(void);
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RCC_ResetSourceTypeDef LHL_RCC_GetResetSource(void);
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void LHL_RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
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ITStatus LHL_RCC_GetPending(uint32_t RCC_IT);
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void LHL_RCC_ClearPending(uint32_t RCC_IT);
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void LHL_RCC_Unlock(void);
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void LHL_RCC_Lock(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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/*********************************End of File**********************************/
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